HDL File Selection

To begin entering or editing a design in HDL, click the HDL Editor icon, which is part of the Design Entry button on the Project Manager's Flow tab. The Editor dialog box displays and presents options for a design file, as shown in the following figure.

• Create new document
  
  
  • Use HDL Design Wizard
    
    Use this option for new designs. The Wizard includes dialogs for you to select the HDL language (VHDL or Verilog), enter the design name, and create ports. When finished, “skeleton” code pops up, complete with the library, entity, ports, and architecture already declared.
    
    
  • Create Empty
    
    Use this option for new designs. This option starts the HDL Editor and displays a blank page.
    
    
• Open
  
  
  • Existing Document
    
    Use this option to select an already existing HDL file.
    
    
  • Active document
    
    Use this option to select from the list of up to the last four active documents.
    
    

Adding the File to the Project

After creating an HDL file for an HDL Flow project, you must “add” the HDL file to the project. You can do this from within the HDL Editor by choosing Project Add to Project. Alternatively, you can add files to the project by selecting Synthesis Add Source File(s) or Document Add from the Project Manager.

In an HDL Flow project, the top level of the design is chosen prior to design “elaboration” in the Synthesis phase. For Verilog, it is not necessary to add files in a specific order. For VHDL, it is important to add the files in the order in which they must be analyzed. Any files depending on the successful analysis of another must appear below that file in the Files tab.

Removing Files from the Project

You can remove files from a project by clicking on the file and selecting Document Remove from the Project Manger.

Note: Removing a file from a project does not erase the file from the disk. It merely removes it from the project.

Getting Help with the Language

The Foundation HDL Editor provides HDL language assistance through both the Language Assistant and the Online Synthesis Documentation. The Language Assistant, shown in the“VHDL Language Assistant” figure, provides templates to aid you in common VHDL logic functions, and architecture-specific features. The “Verilog Language Assistant” figure shows the Verilog Language Assistant that provides templates to aid in for editing Verilog files. The Language Assistant also includes CORE Generator Instantiation templates (see the “CORE Generator Templates in Language Assistant” figure) for modules created with the CORE Generator tool.

To access the Language Assistant, open the HDL Editor, and select Tools Language Assistant.

The HDL Editor also checks syntax. From the HDL Editor, select Synthesis Check Syntax to analyze the file.

Refer to the HDL Editor's online help for more information on the Language Assistant.

Figure 6.1 VHDL Language Assistant

Figure 6.2 Verilog Language Assistant

Figure 6.3 CORE Generator Templates in Language Assistant