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VHDL Reference Guide
Chapter 5: Sequential Statements

if Statements

The if statement executes a sequence of statements. The sequence depends on the value of one or more conditions. The syntax follows.

if condition then 
[ { sequential_statement }
elsif condition then ]
{ sequential_statement }
[ else
{ sequential_statement } ]
end if;

Each condition must be a Boolean expression. Each branch of an if statement can have one or more sequential_statements.

Evaluating Conditions

An if statement evaluates each condition in order. Only the first true condition causes the execution of the if statement's branch statements. The remainder of the if statement is skipped.

If none of the conditions is true and the else clause is present, those statements are executed. If none of the conditions is true and no else clause is present, none of the statements is executed.

The following example shows an if statement. The figure following the example illustrates the corresponding circuit.

signal A, B, C, P1, P2, Z: BIT;

if (P1 = '1') then
Z <= A;
elsif (P2 = '0') then
Z <= B;
else
Z <= C;
end if;

Figure 5.2 Schematic Design for if Statement

Using the if Statement to Infer Registers and Latches

Some forms of the if statement can be used like the wait statement, to test for signal edges and, therefore, imply synchronous logic. This usage causes Foundation Express to infer registers or latches, as described in the “Register and Three-State Inference” chapter.