process Statements

A process statement (which is concurrent) contains a set of sequential statements. Although all processes in a design execute concurrently, Foundation Express interprets the sequential statements within each process one at a time.

A process communicates with the rest of the design by reading values from or writing them to signals or ports outside the process.

The syntax of a process statement follows.

[ label: ] process [ ( sensitivity_list ) ]

     { process_declarative_item }

begin

     { sequential_statement }

end process [ label ] ;

• label, which is optional, names the process.
  
  
• sensitivity_list is a list of all signals (including ports) read by the process, in the following format.
  
  

  signal_name {, signal_name}

  
  
  The circuit Foundation Express synthesizes is sensitive to all signals read the process reads. To guarantee the same results from a VHDL simulator and the synthesized circuit, a process sensitivity list has to contain all signals whose changes require simulating the process again.
  
  Follow these guidelines when developing the sensitivity list.
  
  
  • Synchronous processes (processes that compute values only on clock edges) must be sensitive to the clock signal.
    
    
  • Asynchronous processes (processes that compute values on clock edges and when asynchronous conditions are true) must be sensitive to the clock signal (if any) and to inputs that affect asynchronous behavior.
    
    Foundation Express checks sensitivity lists for completeness and issues warning messages for any signals that are read inside a process but are not in the sensitivity list. An error is issued if a clock signal is read as data in a process.
    
    

    Note: IEEE VHDL does not allow a sensitivity list if the process includes a wait statement.

• process_declarative_item declares subprograms, types, constants, and variables local to the process. These items can be any of the following items, all of which are discussed in the “Design Descriptions” chapter.
  
  
  • use clause
    
    
  • Subprogram declaration
    
    
  • Subprogram body
    
    
  • Type declaration
    
    
  • Subtype declaration
    
    
  • Constant declaration
    
    
  • Variable declaration
    
    

The sequence of statements in a process defines the behavior of the process. After executing all the statements in a process, Foundation Express executes them all again.

The only exception is during simulation; if a process has a sensitivity list, the process is suspended (after its last statement) until a change occurs in one of the signals in the sensitivity list.

If a process has one or more wait statements (and therefore no sensitivity list), the process is suspended at the first wait statement whose wait condition is FALSE.

The circuit synthesized for a process is either combinatorial (not clocked) or sequential (clocked). If a process includes a wait or if signal'event statement, its circuit contains sequential components. The wait and if statements are described in the “Sequential Statements” chapter.

Process statements provide a natural means for describing sequential algorithms. If the values computed in a process are inherently parallel, consider using concurrent signal assignment statements. (See the “Concurrent Versions of Sequential Statements” section of this chapter).

Combinatorial Process Example

The following example shows a process (with no wait statements) that implements a simple modulo-10 counter. The process reads two signals, CLEAR and IN_COUNT, and drives one signal, OUT_COUNT.

If CLEAR is '1' or IN_COUNT is `9', then OUT_COUNT is set to'0.' Otherwise, OUT_COUNT is set to one more than IN_COUNT. The resulting circuit design is shown in the figure following the example.

entity COUNTER is 

   port (CLEAR:      in BIT;

         IN_COUNT:   in INTEGER range 0 to 9;

         OUT_COUNT: out INTEGER range 0 to 9);

end COUNTER;

architecture EXAMPLE of COUNTER is

begin

  process(IN_COUNT, CLEAR)

  begin

     if (CLEAR = '1' or IN_COUNT = 9) then

        OUT_COUNT <= 0;

     else

        OUT_COUNT <= IN_COUNT + 1;

     end if;

  end process;

end EXAMPLE;

Figure 6.1 Modulo-10 Counter Process Design

Sequential Process Example

Another way to implement the counter in the previous example is to use a wait statement to contain the count value internally in the process.

The process in the following example implements the counter as a sequential (clocked) process.

• On each 0-to-1 CLOCK transition, if CLEAR is '1' or COUNT is `9,' COUNT is set to `0.'
  
  
• Otherwise, Foundation Express increments the value of COUNT by one.
  
  
• The value of the variable COUNT is stored in four flip-flops, which Foundation Express generates because COUNT can be read before it is set. Thus, the value of COUNT has to be maintained from the previous clock cycle. For more information on using wait statements and count values, see “wait Statements” section of the “Sequential Statements” chapter.
  
  

The resulting circuit design is shown in the figure that follows the example.

entity COUNTER is 

   port (CLEAR: in BIT;

         CLOCK: in BIT;

         COUNT: buffer INTEGER range 0 to 9);

end COUNTER;

architecture EXAMPLE of COUNTER is

begin

  process

  begin

     wait until CLOCK'event and CLOCK ='1';

     if (CLEAR = '1' or COUNT >= 9) then

        COUNT <= 0;

     else

        COUNT <= COUNT + 1;

     end if;

  end process;

end EXAMPLE;

Figure 6.2 Modulo-10 Counter Process with wait Statement Design

Driving Signals

If a process assigns a value to a signal, the process is a driver of that signal. If more than one process or other concurrent statement drives a signal, that signal has multiple drivers.

The following example shows two three-state buffers driving the same signal (SIG). The resulting circuit design is shown in the figure following the example. To learn to infer three-state devices in VHDL, see “Three-State Inference” section of the “Register and Three-State Inference” chapter.

A_OUT <= A when ENABLE_A else 'Z';

B_OUT <= B when ENABLE_B else 'Z';

process(A_OUT)

begin

   SIG <= A_OUT;

end process;

process(B_OUT)

begin

   SIG <= B_OUT;

end process;

Figure 6.3 Two Three-State Buffers Driving the Same Signal

Bus resolution functions assign the value for a signal with multiple drivers. For more information, see “Resolution Functions” section of the “Design Descriptions” chapter.