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In a synchronous design, all flip-flops use a single clock that is a primary input to the design and there are no combinatorial feedback paths. Synchronous designs perform the same function regardless of the clock rate if all signals can propagate through the design's combinatorial logic during the clock's cycle time.
Foundation Express treats all designs as synchronous. It can therefore change the timing behavior of the combinatorial logic if the maximum and minimum delay requirements are met.
Foundation Express always preserves the Boolean function computed by logic, assuming that the clock arrives after all signals have propagated. Foundation Express' built-in timing verifier helps determine the slowest path (critical path) through the logic, which determines how fast the clock can run.
Foundation Express provides some support for asynchronous designs, but you must assume a greater responsibility for the accuracy of your circuits. Although fully synchronous circuits usually agree with their simulation models, asynchronous circuits might not. Foundation Express might not warn you when a design is not fully synchronous. Be aware of the possibility of asynchronous timing problems.
The most common way to produce asynchronous logic in VHDL is to use gated clocks on latches or flip-flops. The following figure shows a fully synchronous design, a counter with synchronous ENABLE and RESET inputs. Because it is synchronous, this counter works if the clock speed is slower than the critical path. The figure following the example illustrates the design.
entity COUNT is
port(RESET, ENABLE, CLK: in BIT;
Z: buffer INTEGER range 0 to 7);
end;
architecture ARCH of COUNT is
begin
process(RESET, ENABLE, CLK, Z)
begin
if (CLK'event and CLK = '1') then
if (RESET = '1') then -- occurs on clock --edge
Z <= 0;
elsif (ENABLE = '1') then -- occurs on clock --edge
if (Z = 7) then
Z <= 0;
else
Z <= Z + 1;
end if;
end if;
end if;
end process;
end ARCH;
The schematic for the synchronous counter is shown in the following figure.
Figure 8.14 Schematic of Synchronous Counter with Reset and EnableThe following example shows an asynchronous version of the design in the previous example. The version in the following example uses two common asynchronous design techniques.
These techniques work only when the proper timing relationships exist between the reset signal (RESET) and the clock signal (CLK) and there are no glitches in these signals.
The following example shows a design with gated clock and asynchronous reset.
entity COUNT is
port(RESET, ENABLE, CLK: in BIT;
Z: buffer INTEGER range 0 to 7);
end;
architecture ARCH of COUNT is
signal GATED_CLK: BIT;
begin
GATED_CLK <= CLK and ENABLE; -- clock gated by ENABLE
process(RESET, GATED_CLK, Z)
begin
if (RESET = '1') then -- asynchronous reset
Z <= 0;
elsif (GATED_CLK'event and GATED_CLK = '1') then
if (Z = 7) then
Z <= 0;
else
Z <= Z + 1;
end if;
end if;
end process;
end ARCH;
Figure 8.15 Design with AND Gate on Clock and Enable SignalsFigure 8.16 Design with Asynchronous ResetThe following example shows an asynchronous design that might not work, because Foundation Express does not guarantee that the combinatorial logic it builds has no hazards (glitches).
entity COUNT is
port(LOAD_ENABLE, CLK: in BIT;
LOAD_DATA: in INTEGER range 0 to 7;
Z: buffer INTEGER range 0 to 7);
end;
architecture ARCH of COUNT is
begin
process(LOAD_ENABLE, LOAD_DATA, CLK, Z)
begin
if (LOAD_ENABLE = '1') then
Z <= LOAD_DATA;
elsif (CLK'event and CLK = '1') then
if (Z = 7) then
Z <= 0;
else
Z <= Z + 1;
end if;
end if;
end process;
end ARCH;
The design in the previous example works only when the logic driving the preset and clear pins of the flip-flops that hold Z is faster than the clock speed. If you use this design style, you must simulate the synthesized circuit thoroughly. You also need to inspect the synthesized logic, because potential glitches might not appear in simulation. For a safer design, use a synchronous LOAD_ENABLE.
A design synthesized with complex logic driving the gate of a latch rarely works. The following example describes an asynchronous design that never works. The figure following the example shows the resulting schematic.
entity COMP is
port(A, B: in INTEGER range 0 to 7;
Z: buffer INTEGER range 0 to 7);
end;
architecture ARCH of COMP is
begin
process(A, B)
begin
if (A = B) then
Z <= A;
end if;
end process;
end ARCH;
Figure 8.17 Schematic of Incorrect Asynchronous DesignIn the previous example and figure, the comparator's output latches the value A onto the value Z. This design might work under behavioral simulation where the comparison happens instantly. However, the hardware comparator generates glitches that cause the latches to store new data when they should not.