The design flow you use for performing design entry and simulation depends on whether you use schematic design entry or HDL design entry.
In either case, the Xilinx Design Manager graphic interface provides the easiest and most automatic way to implement your design. You can also run the various programs in the design flow manually from a UNIX command prompt. The programs in the Field Programmable Gate Array (FPGA) design implementation flow are described generally in the “Program Options” appendix and described in detail in the Development System Reference Guide.
The programs from the Complex Programmable Logic Device (CPLD) design flow are described in the CPLD Schematic Design Guide and CPLD Synthesis Design Guide.
The Xilinx/Cadence interface supports the following design flows.
The following two figures show the highlights of the design process for FPGA design and CPLD design. Many of the details in both figures are the same except within the blocks labelled “Design Manager Flow Engine” and “Schematic Entry Design Flow.”
Figure 1.1 Overall Cadence Design Flow - FPGA Design |  |
Figure 1.2 Overall Cadence Design Flow - CPLD Design | |
