SIMPRIM Library-Based Functional Simulation

SIMPRIM-based functional simulation requires an NGD file as a starting point. You can use NGDBuild to generate an NGD file from the CONCEPT2XIL EDIF file generated by the CONCEPT2XIL command.

ngdbuild -p XCxxxx design.edf

xxxx corresponds to an architecture, for example, 4000EX, 3000, or part type (for example, 4028ex-pg299-3).

For details on how to use the command line version of NGDBuild, see the “NGDBuild” chapter of the Design System Reference Guide.

For details on using the Design Manager to run NGDBuild, see the “Using the Design Manager” chapter in the Design Manager/Flow Engine Reference/User Guide.

After you create an NGD file, you can conduct a SIMPRIM-Based functional simulation. The next figure illustrates the design flow.

Figure 4.4 SIMPRIM-Based Functional Simulation

The basic simulation steps follow.

1. Use NGD2VER to create a structural Verilog netlist file and a testbench stimulus template.
   
   
2. Copy the testbench stimulus template (designf.tv) to a file named "designf.stim" and use this copy as your user-specified testbench file. For an example of a testbench template file, see the “Sample Test Fixture - XC4000EX Post-NGDBuild Simulation (GSR and GTS simulation)” section of the “Files” appendix.
   
   
3. Run the Verilog-XL simulator in unit delay mode using the Xilinx-supplied Verilog SIMPRIM Library.
   
   

verilog +delay_mode_unit design_namef.stim \
full_path_to_design_namef.v

Using NGD2VER

The NGD2VER program translates your NGD file to a Verilog HDL netlist, which describes the design in terms of Xilinx simulation primitives. This Verilog netlist corresponds to an unmapped design which contains no timing information. You must use NGD2VER with the -tf and -ul options to create the appropriate files for use with the Cadence Verilog-XL simulator.

The following syntax translates your design to a Verilog file.

ngd2ver -tf -ul infile.ngd outfile

• The -tf option generates a testbench template file. The output testbench template/file has a .tv extension. For an example of a testbench template file, see the annotated template in the “Sample Test Fixture - XC4000EX Post-NGDBuild Simulation (GSR and GTS simulation)” section of the “Files” appendix.
  
  
• The -ul option causes NGD2VER to write a `uselib directive pointing to the appropriate simulation library. This directive writes to the output Verilog file, as follows.
  
  `uselib dir= path_to_Xilinx/verilog/src/simprims libext=.vmd
  
  path_to_Xilinx is the location of the Xilinx software.
  
  If you do not specify the -ul option, the `uselib line does not write into the Verilog file. As an alternative to specifying the `uselib directive in your V file, specify the -y and +libext+ options when you invoke Verilog-XL and to specify the path to the simulation library (or libraries) as its argument.
  
  verilog +delay_mode_unit -y \
  $XILINX/verilog/src/simprims +libext+.vmd \
  design_namef.stim full_path_to_design_namef.v
  
  
• infile.ngd is the input .ngd file. If you enter a file name with no extension, NGD2VER searches for a file with an .nga extension having the name you specified. To translate a NGD file, you must enter the NGD extension.
  
  
• outfile indicates the file name to which the output of NGD2VER write. The default is infile.v (infile is the root name of the input file).
  
  

To prevent overwriting an existing Verilog netlist generated by HDL Direct, specify the name of the post-NGDBuild Verilog functional simulation netlist as "infilef.v" as follows.

ngd2ver -tf -ul infile.ngd infilef

This names the output Verilog netlist infilef.v, and the testbench template file, infilef.tv.

Running a Verilog Functional Simulation

Edit a copy of the testbench stimulus template and add your stimulus to it to create a user-specified testbench file.

To run the Verilog simulation, use the procedure described in the “Running the Simulation” section of the “Mixed Mode Designs” section described earlier in this chapter. Use the filenames designf.v and designf.stim as the inputs to your simulation.

Global Reset

The XC3000A/L architecture always contains a GR (Global Reset) port for SIMPRIMS-based functional simulation. However, for Unified library-based functional and timing simulation, GR is hidden for this architecture. Therefore, you cannot use the same testbench file for Unified library simulation and SIMPRIM-based simulation.