After you complete functional simulation, you can implement your design using the Xilinx core tools. The primary netlist format supported by the Xilinx core tools is EDIF 2.0.0, so you must first convert your design into a .edf file using the CONCEPT2XIL command line script.
The Xilinx Development implementation tools currently support XNF format netlists. However, Xilinx plans to discontinue this support in future releases.
After you create a .edf file, you can then use either the NGDBuild command or the Xilinx Design Manager to generate an NGD file. You can then implement your design with Xilinx Design Manager. See the Design Manager/Flow Engine Reference/User Guide for details. You can also use the Xilinx command line versions of the individual tools to implement your design from a UNIX shell. Refer to the Development System Reference Guide for details on FPGA designs. For CPLD designs, refer to the CPLD Schematic Design Guide.
Xilinx implementation tools first translate the design into a flattened or hierarchical netlist, then optimize, place, and route the design. The tools annotate delay data for timing simulation and generate physical (bitstream) design data for downloading. See the “FPGA Design Implementation” figure for an overview of the process for FPGAs. See the “CPLD Design Implementation” figure for an overview of the process for CPLDs.
This chapter contains the following sections.
Figure 5.1 FPGA Design Implementation |  |
Figure 5.2 CPLD Design Implementation | |
This chapter additionally describes how to convert your Concept Verilog file into an EDIF file using CONCEPT2XIL. The chapter also provides specific references to the command line design implementation tools for FPGAs and CPLDs.
