This section describes Unified Library based functional simulation for pure Concept schematic designs and Concept designs with LogiBLOX modules.
The functional simulation of a pure schematic design requires that you enable HDL Direct when you save the various schematic blocks in your design. With HDL Direct enabled, a Verilog HDL view automatically generates for a schematic or symbol body when you save it. You then run CONCEPT2XIL with the -sim_only option to resolve the design hierarchy and generate the required design.vf Verilog configuration file and design.v file containing the required global modules.
Use the following steps to functionally simulate a design.
When you save a schematic in Concept with HDL Direct enabled, Concept creates a directory for the schematic with an underlying logic/ directory. The logic/ directory contains a Verilog HDL view for that block of your design. You must then run CONCEPT2XIL -sim_only to generate the required files for functional simulation.
The following shows the CONCEPT2XIL syntax.
concept2xil -family technology -sim_only design_name
The -family option specifies the library to use (for example, xce4000x). To target the Xilinx XC4000EX, XC4000XL and XC4000XV architectures, specify "xce4000x" as the target library.
The -sim_only option tells CONCEPT2XIL to generate only the files needed for functional simulation.
The CONCEPT2XIL program generates the following two files in the Xilinx run directory (default is xilinx.run).
The configuration file, design.vf, contains information on the location of the Verilog netlists for each block of the design.
The design.v file defines the following modules. CONCEPT2XIL does not support these modules, but nevertheless writes them using the embedded Cadence EDIF netlist writer.
You also need to create a testbench file in a text editor for your functional simulation, usually named design.stim.
This document uses the terms "testbench" and "test fixture" interchangeably.
In the M1.5 Verilog interface, a new methodology supports the global (set/) reset and global tri-state signals in the FPGAs, and global reset in the CPLDs. The “Setting Global Set/Reset and Tri-state Signals (FPGAs)” section of the “Design and Simulation Techniques” chapter describes this procedure in detail. Most requirements implement automatically when you use the testbench template generated by NGD2VER. However, performing Unified Library functional simulation directly from CONCEPT2XIL does not automatically generate a testbench template. You can either create the testbench file manually, or, as a workaround, process your design through NGDBuild. You then run NGD2VER -tf -ul on the design.ngd file to generate a template that you can use for your testbench, as in the following example.
ngdbuild -p 4028ex-3-pg299 design
ngd2ver -tf -ul design.ngd
For an example of a testbench file, see the “Sample Test Fixture - XC4000EX Unified Library Functional Simulation (GSR and GTS simulation)” section of the “Files” appendix.
To functionally simulate the design with Verilog-XL, you must do the following.
verilog +delay_mode_unit design.stim \
full_path_to_design_name.v \
-f full_path_to_design_name.vf
(The “\”at the end of a line indicates that you can type the line following the current one on the same command line.)
If available, specify the +gui option to invoke the Verilog Environment. (The 97A release supports the +gui option.)
In the following figure, the Verilog-XL Control Window (VCW) displays when you use the +gui option.
Figure 4.2 Part of the Verilog Environment |  |
To conveniently run a Verilog simulation, create a script containing a command line with all the required options. To run the simulation, simply invoke the script as described in the following example.
For a design named “calc,” targeting an XC4000XL component, assume you generate a Verilog netlist called “calc.v” with CONCEPT2XIL and create a testbench file called “calc.stim.” Assume your simulation library resides in the directory, $XILINX/cadence/data/verilogxce4000x.
To run a functional simulation, navigate to the xilinx.run directory and run the simulation using this command line.
verilog +delay_mode_unit calc.stim calc.v \
-f calc.vf
To specify the simulation library, $XILINX/cadence/data/verilogxce4000x, you can add the following `uselib directive to your .v file.
`uselib dir = explicit_path_to_Xilinx/cadence/data/verilogxce4000x libext=.v
Or, you can specify the library path as a -y command line option to Verilog-XL.
A waveform display application separate from Verilog-XL displays your simulation waveforms. Given the appropriate directives, Verilog-XL writes the waveform data to a simulation history directory (design.shm). The waveform viewer application (usually SimWave) reads this data from the simulation history database and displays the waveforms.
If you wish to view your simulation waveforms graphically while performing your functional simulation, you must add an “initial” block to the testbench file containing directives to create a simulation history database for the waveform viewer.
NGD2VER adds this “initial” block to a stimulus template file (designf.tv) when invoked with the -tf option. For pre-NGDBuild functional simulation flows, you must add this block to your testbench manually.
The following shows a sample "initial" block adding Simulation History Manager support.
initial
begin
$shm_open(“calc.shm”);
$shm_probe(“AS”);
endThe $shm_open command creates the database directory, “calc.shm.” $shm_probe(“AS”) directs the simulation history manager to probe all signals, thus making them available for viewing in the waveform viewer.
To invoke SimWave do one of the following.
For a complete description of SimWave, refer to the “Using SimWave” section of the “Schematic Design Tutorial” chapter.
Always toggle global reset at the beginning of a simulation to ensure that all flip-flops and latches initialize to a known state. See the “Setting Global Set/Reset and Tri-state Signals (FPGAs)” section of the “Design and Simulation Techniques” chapter for information on toggling global reset for Spartan/XL, XC3000A/L, XC3100A/L, XC4000/E/EX/XL/XV, XC5200, and XC9500 devices.
Refer to the “Processing Designs with LogiBLOX Components” appendix for detailed information.
Functionally simulate mixed mode designs using a slightly different flow. For designs with schematic top levels, make each non-schematic block (from Synopsys or other third party tool) available in, or processed down to XNF, NGO, or EDIF format. Represent each non-schematic block with its own body (or symbol) in the design schematics, using the following steps.
ngd2ver -tf -ul design_name
The -tf option generates a testbench template file (TV) for you containing an instantiation of your design as well as support for the Cadence Simulation History Manager.
Make a copy of this testbench file, name it (designf.stim), and use it as a starting point for your simulation stimulus. For an example of a testbench file, see the “Sample Test Fixture - XC4000EX Post-NGDBuild Simulation (GSR and GTS simulation)” of the “Files” appendix.
The -ul option directs NGD2VER to write out a `uselib directive which tells Verilog-XL where to load the SIMPRIM based simulation libraries when compiling the simulation.
See the “Design and Simulation Techniques” chapter for information on driving the global signals GSR, GR, GTS and PRLD.
To functionally simulate the design with Verilog-XL, you must do the following.
verilog +delay_mode_unit design_namef.stim \
full_path_to_design_namef.v
(The “\”at the end of a line indicates that you can type the line following the current one on the same command line.)
If available, specify the +gui option to invoke the Verilog Environment.
The following figure shows the Verilog-XL Control Window (VCW) that displays when you use the +gui option.
Figure 4.3 Verilog-XL Control Window | |
To conveniently run the simulation, create a script containing a command line with all the required options. To run a simulation, simply invoke the script as shown in the following example.
For a design named “calc,” targeting an XC4000EX component, assume you generate a Verilog netlist called “calcf.v” with NGD2VER, and create a testbench file called “calcf.tv.”
ngd2ver -tf -ul calc.ngd calcf
Copy the testbench template file "calcf.tv" to a file named "calcf.stim."
To run a functional simulation, navigate to the xilinx.run directory and enter the following command.
verilog +delay_mode_unit calcf.stim calcf.v
To invoke SimWave, enter the following command.
simwave &
If using the Verilog-XL GUI, you can invoke SineWave by clicking on the Waveform View button.
For a complete description of SimWave, refer to the “Using SimWave” section of the “Schematic Design Tutorial” chapter.
Always toggle global reset at the beginning of a simulation to ensure that all flip-flops and latches initialize to a known state. See the “Setting Global Set/Reset and Tri-state Signals (FPGAs)” section of the “Design and Simulation Techniques” chapter for information on toggling global reset for Spartan/XL, XC3000A/L, XC3100A/L, XC4000/E/EX/XL/XV, XC5200, and XC9500/XL devices.
The XC3000A/L architecture always contains a GR (Global Reset) port for SIMPRIMS-based functional simulation. However, for Unified library-based functional and timing simulation, GR is hidden for this architecture. Therefore, you cannot use the same testbench file for Unified library simulation and SIMPRIM-based simulation.
