Converting the Concept Design to an EDIF File

After completing your Concept schematic, you must convert the Verilog file (.v) that it outputs into an EDIF file before you can use the Xilinx design implementation tools. To translate the Verilog file, you must run the CONCEPT2XIL command line utility. The design flow for this conversion appears in the “CONCEPT2XIL Design Flow” figure.

Figure 5.3 CONCEPT2XIL Design Flow

The following shows the syntax for the CONCEPT2XIL command.

concept2xil [-cdslib lib_map_filename]
   [-gcmd command_filename] [-help] [-log log_filename]
   [-rundir run_directory] -family technology design_name

• -cdslib lib_map_filename indicates the name of the library map file, which points to a technology-specific VAN-compiled Verilog library or libraries whose Verilog names are of the form xcexxx_syn. The default is cds.lib. This parameter is optional.
  
  
• -gcmd command_filename specifies the name of the global.cmd command file, which indicates the Concept libraries available to the netlister. The default is global.cmd. This parameter is optional.
  
  
• -help allows you to obtain more information on CONCEPT2XIL and its options.
  
  
• -log log_filename specifies the name of the log file. The default is concept2xil.log. This parameter is optional.
  
  
• -rundir run_directory specifies the name of the directory in which CONCEPT2XIL is run. The default is xilinx.run. This parameter is optional.
  
  
• -family technology specifies the target architecture. Valid technologies are xce3000, xce4000e, xce4000x, xce5200, and xce9000. This parameter is optional.
  
  
• design_name is the input design name.
  
  

Enter this command as shown in the following example.

concept2xil -family xce4000x block

NOTE

The CONCEPT2XIL command also generates a V file and a VF file as well as an EDIF file. It overwrites any existing V and VF files with the same name in the destination directory. Ensure you do not overwrite any existing files that you want to preserve.

After generating an EDIF file, you can use the Xilinx design tools to implement your design.

If targeting a Spartan or SpartanXL device, refer to the Xilinx web page, (http://www.xilinx.com/techdocs/3830.htm), or the A1.5 release notes for the latest details about using CONCEPT2XIL for these device families.