Functional Simulation

This section briefly describes the steps for running Unified Library Based and SIMPRIM-based functional simulation.

Unified Library Based Functional Simulation

You can conduct Unified Library-based functional simulation only on pure schematic designs without LogiBLOX elements.

Schematic Designs Without LogiBLOX Elements

Use the following steps to simulate schematic designs without LogiBLOX elements.

1. Enable HDL Direct in Concept.
   
   
2. Save the schematic in Concept.
   
   
3. Run concept2xil -sim_only with the following syntax.
   
   concept2xil -family technology -sim_only design_name
   
   This command creates a V and VF file in the xilinx.run directory unless specified otherwise using the -rundir option.
   
   
4. Run the functional simulation using Verilog-XL.
   
   

verilog +delay_mode_unit full_path_to_design_name.v \
-f full_path_to_design_name.vf design_name.stim

SIMPRIM Library Based Functional Simulation

SIMPRIM-based functional simulation requires an NGD file as an input. You can use NGDBuild to generate a NGD file from an EDIF, XNF, or NGO file.

1. Submit the design to NGDBuild.
   
   ngdbuild -p part_type design_name
   
   You do not need to specify the part_type with the -p option if the schematic in the CONFIG block specifies PART.
   
   
2. Use NGD2VER to create a structural Verilog netlist and a testbench stimulus template. Specify the output netlist name as design_namef to avoid overwriting any Unified Library simulation netlists.
   
   ngd2ver -tf -ul design_name.ngd design_namef.v
   
   
3. Make a copy of the testbench stimulus template and name it designf.stim. Edit the copy of the testbench file to create a user-specified testbench file.
   
   
4. Run the Verilog-XL command.
   
   

verilog +delay_mode_unit  full_path_to_designf.stim \
full_path_to_designf.v

(The “\”at the end of a line indicates that you can type the line following the current one on the same command line.)

Mixed Mode Designs

Perform functional simulation of mixed-mode schematic designs containing SXNF, XNF, or EDIF sub-blocks using the Xilinx architecture-independent Verilog SIMPRIM simulation libraries. More generally, perform SIMPRIM library functional simulation on any type of design regardless of the design entry method. Use the following procedure.

1. Generate an XNF or EDIF netlist for each non-schematic block using the appropriate translation tool. For example, write out a Synopsys block in SXNF or SEDIF format.
   
   
2. Run NGDBuild to merge the schematics with the non-schematic blocks.
   
   ngdbuild -p part_type design_namef
   
   
3. Proceed to Step 2 of the “SIMPRIM Library Based Functional Simulation” section.