Design Implementation

This section explains how to implement schematic designs for FPGAs and CPLDs.

UCF Files

When writing UCF files to signal names or instance names in component sub-modules, pay attention to how CONCEPT2XIL writes out hierarchy references. With respect to the top-level sheet, CONCEPT2XIL issues a “page1$” in its hierarchy. For example, you could specify the following in the UCF file.

NET "page1$ufastcnt/qxo3" S;

This correlates to the references written in the .edf file. To verify this, open Epic and view all the nets to their names, or open the EDIF file in a text editor to view the signal or instance names.

Schematic Designs (FPGA)

1. Convert the Concept design from Cadence to EDIF with CONCEPT2XIL, as shown in the following example.
   
   concept2xil [-cdslib lib_map_filename] \
   -family technology design_name
   
   The EDIF file writes to a xilinx.run directory by default.
   
   Refer to the “Converting the Concept Design to an EDIF File” section of the “Design Implementation” chapter for details.
   
   
2. Navigate to the xilinx.run directory and submit the design to NGDBuild. NGDBuild reads a file in EDIF or XNF format, reduces all the components in the design to Xilinx primitives, runs a logical design rule check on the design, and writes an NGD file as output.
   
   ngdbuild -p technology design_name
   
   For example you can enter either of the following.
   
   ngdbuild -p xc4000ex test
   
   or
   
   ngdbuild -p 4028exhq240-3
   
   You do not need to specify the -p part type if it is specified in the schematic.
   
   
3. Map the logic to the components in the FPGA by typing the following syntax.
   
   map -p partname design_name.ngd
   
   The following provides a detailed example of this syntax.
   
   map -p 4028exhq240-3 test.ngd
   
   You do not need to specify the -p part type if it is specified in the schematic or as an option to NGDBuild.
   
   
4. Place and route the design.
   
   par test.ncd testt.ncd
   
   The MAP utility creates the first file and PAR creates the other one.
   
   
5. Proceed to the “Post-Implementation Timing Simulation” section.
   
   
6. Run BitGen.
   
   

The BitGen program produces a bitstream for Xilinx FPGA device configuration. After the FPGA design completely routes, configure the device so that it can execute the desired function. Accomplish this configuration using the bitstream generated by BitGen, Xilinx's bitstream generation program. BitGen takes a fully routed NCD file as its input and produces a configuration bitstream - a binary file with a .bit extension.

Schematic Designs (CPLD)

When using CPLDs, use the following procedure for implementing pure schematic designs, designs with XNF, EDIF, or NGO elements, and mixed-mode schematic-at-top designs.

1. Convert the Concept design from Cadence to EDIF with CONCEPT2XIL.
   
   concept2xil [-rundir run_directory]
   -family technology design_name
   
   Refer to the “Converting the Concept Design to an EDIF File” section of the “Design Implementation” chapter for details.
   
   
2. Submit the design to the CPLD fitter.
   
   cpld -p partname design_name
   
   
3. Proceed to the “Post-Implementation Timing Simulation” section.
   
   

HDL Top Level Designs

1. Synthesize the HDL modules in your design treating any non-HDL sub-blocks as black boxes and write out an EDIF or XNF file from the synthesis tool.
   
   
2. Process any instantiated sub-blocks down to EDIF, XNF, or NGD format. Merge all the EDIF, XNF, and NGO files for the submodules with the top level XNF or EDIF file by running NGDBuild.
   
   ngdbuild -p part_number design_name
   
   You can use either of the following examples.
   
   ngdbuild -p XC4000E test
   
   ngdbuild -p 4028exhq240-3 test
   
   test is the root name for the .edf or .xnf file.
   
   
3. Proceed to the “Post-Implementation Timing Simulation” section.
   
   

Pure HDL Designs

1. Synthesize the HDL file and create an EDIF or XNF file for the synthesized design.
   
   
2. Convert the EDIF or XNF file to an NGD file using NGDBuild.
   
   ngdbuild -p technology design_name
   
   ngdbuild -p part_number design_name
   
   The following examples show the detailed syntax.
   
   ngdbuild -p XC4000E test
   
   ngdbuild -p 4028exhq240-3
   
   test is the root name for the EDIF or XNF file.
   
   
3. Proceed to the “Post-Implementation Timing Simulation” section.