Performing Timing Simulation

Timing simulation uses the block and routing delay information from the routed design to give a more accurate assessment of the behavior of the circuit under worst-case conditions. In this section, you again invoke Verilog-XL and SimWave to display the timing data.

Invoking Verilog-XL for Timing Simulation

In your xilinx.run directory you now have three files called “time_sim.” This V file contains a complete Verilog netlist of the Calc design, broken down to the Xilinx SIMPRIM library primitives. The SDF file contains all the net delays, and you need this file if you want a non-unit delay timing simulation. NGD2VER (called by Design Manager) also created a TV file, a test fixture template. Although you can modify this template to add your own input stimuli, in most cases you can re-use the functional simulation test fixture you created earlier (calcf.stim in this tutorial). However, before doing so, you must comment out the line that specifies the GSR_SIGNAL macro in your calcf.stim file. You comment out this line because the Verilog netlist for a post-NGDBuild or routed design already models the connection to the GSR net, and the definition causes contention problems during your simulation. In the Calc tutorial design, the specific line in calcf.stim that needs commenting out follows.

      `define GSR_SIGNAL test.uut.gblreset.

1. Enter the following on the UNIX command line.
   
   verilog calct.stim time_sim.v
   
   The .sdf file reads in automatically because of the “$sdf_annotate” command inside the time_sim.v file.
   
   
2. The output resembles that you encountered in functional simulation, except that the displayed times do not always show as 50ns increments.
   
   
3. Invoke SimWave, and go to File Restore Setup. Enter the name of the .wrf file you created when you saved the setup under functional simulation (calc.wrf). The resulting waveforms look similar, but now contain precise timing information.