Examining Routed Designs with EPIC

NOTE

This section applies only to FPGA designs. If targeting a CPLD such as an XC9500 device, skip to the “Making Incremental Design Changes” section.

At this point in the tutorial, you completed the design process. To see how the Xilinx software implements your design, take a graphic look at your placed and routed design using the Editor for Programmable Integrated Circuits, or EPIC. You can access EPIC from the Xilinx Design Manager.

EPIC provides several useful functions.

• Manual editing of a routed design
  
  
• Probe insertion during in-circuit verification
  
  
• Static timing analysis
  
  

A separate tutorial explains how to use EPIC. See the “EPIC Tutorial” chapter of the EPIC Reference/User Guide. Before starting this tutorial, select the ver1 rev1 revision of the design in the project view.