Appendix A

Cadence Concept and Verilog Interface Notes

This appendix provides information on setting up the Cadence Concept interface for schematic entry, and Verilog-XL for simulation. Included are recommendations on methods for locking pins and entering timing constraints. This appendix contains the following sections.

• “Documentation”
  
  
• “Setting Up the Cadence Interface”
  
  
• “Cadence/Verilog Design Flow”
  
  
• “Setting Up for Concept”
  
  
• “Using HDL Direct”
  
  
• “Iterated Instances Versus Size Support”
  
  
• “Starting Concept”
  
  
• “Functional Simulation”
  
  
• “Translating a Design to EDIF”
  
  
• “Timing Simulation”
  
  
• “Support for Board Level Simulation”
  
  
• “Pin Locking”
  
  
• “Timing Constraints”
  
  

Documentation

The following documentation is available for the Cadence interface.

• The Xilinx Cadence Interface/Tutorial Guide is available on the Alliance Series Documentation CD-ROM supplied with your software.
  
  
• The Cadence software documentation (for Cadence applications such as Concept and Verilog-XL) is available from Cadence in an online format. You can view it by entering the following on the UNIX command line.
  
  openbook
  
  
• The Xilinx Release Documentation describes current issues regarding the use of the Cadence interface.
  
  

Setting Up the Cadence Interface

In addition to the environment variables described in the “Installing the Software” chapter, the following environment variables must be modified or added to run the Cadence interface tools.

• CDS_INST_DIR (add for Concept)
  
  
• VERILOGEXE (add for Verilog-XL)
  
  
• XAPPLRESDIR (add for Verilog-XL)
  
  
• XNLSPATH (modify for Verilog-XL)
  
  
• XKEYSYMDB (modify for Verilog-XL)
  
  
• path (modify)
  
  
• LD_LIBRARY_PATH (modify for Solaris)
  
  
• SHLIB_PATH (modify for HP/UX)
  
  
• LIBPATH (modify for IBM RS6000)
  
  

Set these variables as follows.

setenv CDS_INST_DIR installation_path_to_cadence

setenv VERILOGEXE $CDS_INST_DIR/tools/verilog/bin/verilog

setenv XAPPLRESDIR $CDS_INST_DIR/tools/verilog/etc

setenv XNLSPATH $CDS_INST_DIR/tools/verilog/etc/nls:$XNLSPATH

setenv XKEYSYMDB $CDS_INST_DIR/tools/verilog/etc/XKeysymDB:$XKEYSYMDB

set path = ($CDS_INST_DIR/tools/bin $CDS_INST_DIR/tools/pic/picdesigner/bin $CDS_INST_DIR/tools/editor/lib $CDS_INST_DIR/tools/dfII/bin $path)

For Solaris only.

setenv LD_LIBRARY_PATH $CDS_INST_DIR/tools/lib: $CDS_INST_DIR/tools/verilog/lib: path_to_x11_libs:
/usr/lib:$OPENWINHOME/lib:$LD_LIBRARY_PATH

For HP/UX only.

setenv SHLIB_PATH $CDS_INST_DIR/tools/lib: $CDS_INST_DIR/tools/verilog/lib:/usr/lib:/lib: path_to_x11_libs: $SHLIB_PATH

For IBM RS6000 only.

setenv LIBPATH $CDS_INST_DIR/tools/lib:$CDS_INST_DIR/tools/verilog/lib:/usr/lib:/lib:$LIBPATH

It is common to create a soft link called “tools” under $CDS_INST_DIR, and to link it to the directory $CDS_INST_DIR/tools.<platform>, where platform is “hppa” (for HP7), “sun4v” (for Solaris), or “ibmrs” (for IBM RS6000). If your Cadence tool directory is not set up in this way, then substitute “tools.platform” where you see “tools” previously, as shown in the following example.

setenv CDS_INST_DIR /products/cds.ver97a

setenv VERILOGEXE $CDS_INST_DIR/tools/verilog/bin/verilog

setenv XAPPLRESDIR $CDS_INST_DIR/tools/verilog/etc

setenv XNLSPATH $CDS_INST_DIR/tools/verilog/etc/nls:$XNLSPATH

setenv XKEYSYMDB $CDS_INST_DIR/tools/verilog/etc/XKeysymDB:$XKEYSYMDB

setenv LD_LIBRARY_PATH $CDS_INST_DIR/tools/lib: $OPENWINHOME/lib : /usr/lib :/tools/x11r5/sun5/lib: $LD_LIBRARY_PATH

set path = ($CDS_INST_DIR/tools/bin \ 
   $CDS_INST_DIR/tools/pic/picdesigner/bin \
   $CDS_INST_DIR/tools/editor/lib \
   $CDS_INST_DIR/tools/dfII/bin \
   $path)

NOTE

The previous settings assume that the XILINX and LD_LIBRARY_PATH environment variables point to the appropriate areas.

Cadence/Verilog Design Flow

The following figure illustrates how Cadence Concept and Verilog-XL interact with the Xilinx Software. The design flow shows design entry, functional simulation, implementation, and timing simulation. The design is entered into Concept, using the appropriate HDL Direct library (hdl_direct_lib) and the appropriate Xilinx Concept library for the device architecture. If the design is purely schematic, it can then be passed to Verilog-XL for functional simulation after analyzing it with Concept 2XIL.

NOTE

The “Top Portion of Figure A-1” figure and the “Bottom Portion of Figure A-1” figure are enlarged versions of the “Cadence/Verilog Interface Design Flow” figure.

Figure A.1 Cadence/Verilog Interface Design Flow

Figure A.2 Top Portion of Figure A-1

Figure A.3 Bottom Portion of Figure A-1

• Once the design is verified, the Concept schematic is processed by CONCEPT2XIL to create an EDIF (EDF) file.
  
  
• If the design contains non-schematic blocks, then functional simulation may be performed after NGDBuild is completed. All designs can be simulated at this point since non-schematic blocks, if any exist, are merged together by NGDBuild.
  
  
• The EDF file is passed to the Xilinx Alliance Series Design Implementation Tools (Design Manager Flow Engine) for implementation.
  
  
• The Xilinx implementation tools create a structural back-annotated Verilog file for timing simulation, and can optionally create a template test fixture file.
  
  
• Simulation vectors are added to a copy of the test fixture template, then the Verilog netlist and the test fixture are passed to Verilog-XL for timing simulation.
  
  

Setting Up for Concept

To set up your system for Concept, you must have the global.cmd, master.local, and cds.lib files in the design directory. Refer to the Cadence Interface/Tutorial Guide for more information.

Global.cmd File

You need a global.cmd file that references the proper libraries. The following is a sample global.cmd file.

master_library "./master.local" ;

library "xce4000x" ,

        "xcepads",

        "hdl_direct_lib",

        “standard” ;

use "my_design.wrk" ;

root_drawing "my_design" ;

The entries following the “library” reference are aliases to libraries from which you can access components for your design, in addition to those listed in $CDS_INST_DIR/lib/master.lib.

One of the entries in the “library” reference must point to the Xilinx family of devices you are using. In this example, the “xce4000x” alias points to the XC4000X (XC4000 EX/XL/XV) family library. The explicit path to each library is defined in master.local. Note the presence of “hdl_direct_lib”; this is required for HDL Direct Support. The “xcepads” library contains the Xilinx pad symbols. The “use” line points to a file (typically with a .wrk extension) that Concept can use to store references to blocks which are specific to your design. If your global.cmd file has a “use” directive specifying a .WRK file, Concept will create the specified file for you if it does not already exist (as in the case of a new design).

Master.local File

The master.local file contains the actual UNIX path to the libraries referenced in global.cmd. It does not need to contain the path to libraries that are local, or which are standard Cadence-supplied libraries specified in $CDS_INST_DIR/lib/master.lib. The following is an example master.local file for an XC4000X design.

file_type = master_library;

"xce4000x" '/xilinx/cadence/data/xce4000x/ 
   xce4000x.lib';

"xcepads" '/xilinx/cadence/data/xcepads/ xcepads.lib';

end.

Do not use variables (such as $XILINX) in this file; absolute path names are required.

Cds.lib File

This file is required by Concept2XIL, and it must point to the location that contains the VAN (Verilog Analyzer)-compiled Verilog library files. As an example, here is a sample cds.lib file for a 4000X design.

define xce4000x_syn /xilinx/cadence/data/ xce4000x_syn

The format for entries in this file is as follows.

define target_tech_syn path_to_XILINX/cadence/data/target_tech_syn

where target_tech is spartan, spartanxl, xce3000, xce4000e, xce4000x, xce5200 or xce9000.

Using HDL Direct

The Xilinx/Cadence Interface does not support SCALD methodology for design entry. HDL Direct design methodology is required. HDL Direct must be enabled whenever a schematic sheet is saved. Putting the following commands in your startup.concept file will activate HDL Direct every time Concept is invoked.

set hdl_direct on

set hdl_checks on

set check_signames on

set check_net_names_hdl_ok on

set check_port_names_hdl_ok on

set check_symbol_names_hdl_ok on

set capslock_off

runopl installation_path_to_cadence/tools/fet/ concept/hdl_direct/bin/autosym

When processing designs entered using SCALD methodology, refer to Appendix C of the HDL Direct User Guide (from Cadence) for complete information on converting these designs for HDL Direct compliance.

Iterated Instances Versus Size Support
The Cadence Interface and Libraries do not support the SIZE property. Iterated instances should be used instead (which essentially consist of adding a bus index to the PATH attribute of the symbol body instance). Refer to the Cadence HDL Direct User Guide for more information.

Starting Concept
To start the Concept editor, enter the following.
concept &

Functional Simulation
This section describes functional simulation of your designs.

Testfixture: Asserting the Global Set/Reset in a Pre-NGDBuild Unified Library Functional Simulation
In a netlist for a Spartan, SpartanXL, XC4000E/EX/XL/XV design that uses STARTUP, the Global Set and Reset (“GSR”) net that leads to every flip-flop is connected to the STARTUP block implicitly. Toggling the signal that controls the GSR pin is needed to begin simulation and to simulate resetting the device. Even if your design does not utilize the STARTUP block, the GSR line should be pulsed once at the beginning of simulation to simulate the initial behavior of the device.
In the Unified Library functional simulation, if the design contains a STARTUP block, you must connect the logic that controls the GSR pin on the STARTUP block to the underlying global GSR net by using a `define directive to specify a macro called “GSR_SIGNAL.”
`define GSR_SIGNAL
   testfixture.design_instance_name.signal_on_GSR_pin
Here testfixture is the name of the testfixture module, design_instance_name is the instance name of the instantiated design, and signal_on_GSR_pin is the net name that sources the STARTUP GSR pin.
The signal that actually hooks up to the STARTUP GSR pin should be used. In your testfixture, you may proceed to assign values to the input pin that you use as your global reset (you do not have to assign values to the actual attached STARTUP block GSR pin signal). For example, assuming “global_reset” is the name of the port controlling the GSR pin on the STARTUP symbol.
module my_testfixture(input_net, output_net, global_reset);     

`define GSR_SIGNAL my_testfixture.uut.signal_on_GSR_pin 

my_design uut (.in(input_net), .out(output_net), .global_reset(global_reset))

reg input_net, global_reset;

initial begin
   global_reset=1; 
   #300  global_reset=0;
  //assign inputs 
However, if the STARTUP block is not used, you must directly drive the GSR. You may again use the `define directive to define a GSR signal, even though it does not explicitly exist in the schematic or HDL code. To do this, you would define a dummy Verilog register “reg test.GSR” (assuming the testfixture module name is “test”, which is a name we recommend if you want to reuse the testfixture with post-NGDBuild simulation). You then need to use the `define to hook it up to the verilog models, and drive “test.GSR” in your stimulus.
reg test.GSR;
`define GSR_SIGNAL test.GSR
.....
.....
initial begin
   test.GSR=1
   #300 test.GSR=0;
   //assign inputs now

For the 5200 family (which has a STARTUP symbol available), there is a global reset signal called “GR,” use.

`define GR_SIGNAL testfixture.design.signal_on_GR_pin


instead. If you are not using STARTUP, then you must define a dummy signal, as previously discussed.


For the 9500 family, to model the global PRLD signal, use the following.

reg PRLD 


//no 9K STARTUP, so use this dummy register value


`define PRLD_SIGNAL test.PRLD


.....


.....


initial begin


  test.PRLD=1;


  #300 test.PRLD=0;


  //assign inputs now



For the 3000A family, use the following.

reg GR; //no 3K STARTUP, use this example.


`define GR_SIGNAL test.GR


Use a similar procedure as previously described for the 9500. (Note that GR on an XC3000A is active-Low.)




Schematic Functional Simulation
You can functionally simulate your design before translating it if the design is purely schematic (no “black boxes” in your design). Assuming that HDL Direct was activated when the schematic was saved, you should run.
concept2xil -sim_only -family target_tech design_name
This command creates a .V and .VF (Verilog configuration file) file in your xilinx.run directory (or optionally the directory specified with the -rundir parameter). You must create a test fixture file (.tv) manually. 
An example of a complete flow is as follows.
concept2xil -sim_only -family xce4000x my_design
Go to the xilinx.run directory, and create a test fixture file in a text editor, “my_testfixture.stm,” for example, then run your Verilog-XL simulation by entering
verilog +delay_mode_unit my_testfixture.stim my_design.v -f my_design.vf 
For more information, refer to the Cadence Interface/Tutorial Guide.

Post-NGDBuild Functional Simulation
If the design has blocks that have no schematics underneath (a block of HDL code, for instance), then it is necessary to compile each non-schematic block to either an NGO, EDIF or XNF file and to simulate after the Xilinx program NGDBuild has merged all the formats into one NGD file. Briefly, the flow is as follows.
concept2xil -family target_tech design_name
cd xilinx.run
ngdbuild-p part_name design_name
ngd2ver -ul -tf design_name.ngd
verilog +delay_mode_unit test_fixture.stim design_name.v

Translating a Design to EDIF
To translate a Concept design into an EDIF file for the Xilinx implementation tools to use, enter the following command.
concept2xil -family target_tech design_name
For example, to target my_design to the XC4000X technology.
concept2xil -family xce4000x my_design
The Concept2XIL program will by default put its output in the directory xilinx.run (this will be created automatically if it does not exist). You may change this to a different directory by using the -rundir option on the Concept2xil command line.
NOTE
The Concept2XIL program is only compatible with the Xilinx Concept libraries (xce***) where *** = target architecture. For example of a Xilinx Concept Library name: xce9000.

Timing Simulation
After implementing your design (that is, after running MAP and PAR on your design) and generating an annotated NGA netlist (with NGDANNO), you must use NGD2VER to generate a structural Verilog netlist and SDF file (Standard Delay Format) that Verilog-XL can use.
For example, for the design “my_design”, enter the following.
ngd2ver -ul -tf -pf my_design.nga
This creates a .V, .SDF and .TV file. The -ul option causes NGD2VER to automatically add a “uselib” directive to the .V file that references the Xilinx-supplied Verilog SIMPRIM libraries.
The -tf option causes NGD2VER to automatically create a test fixture template file, which is named my_design.tv. You may either edit the .TV file to add the appropriate stimuli, or, in most cases, you should be able to re-use your functional simulation test fixture file.
If you re-use your functional simulation test fixture file and your design contains a STARTUP block, and the GSR, GTS or both pins on the STARTUP block are connected to a signal, you will need to make one modification to the test fixture--the GSR_SIGNAL, GTS_SIGNAL, or both) macro(s) must be commented out.
// `define GSR_SIGNAL test.uut.signal_on_GSR_pin.
If you need to integrate the design into a board level schematic, you must also specify the -pf option to NGD2VER to obtain a .pin file for XIL2CDS.
To run the simulation, type.
verilog my_testfixture.stim my_design.v
Verilog-XL automatically reads in the .sdf file, since there will be a reference to it in the .V file. 

Support for Board Level Simulation
Cadence ships the program XIL2CDS to produce the chips_prt, and body file needed to integrate the Xilinx FPGA or CPLD into a Concept board level simulation.
Typical syntax is as follows.
xil2cds routed_design -lwbverilog

-use name_of_.wrk_file -r run _directory

-family xce4000ex -mode all
In the following example, design name is “my_design_r”, .WRK file is design.wrk, run directory is the current directory, architecture is XC4000X, -mode option specifies that all pins on the package be represented on the design body file, and -pkg specifies the location of the package pin file.
xil2cds my_design_r -lwbverilog -use design.wrk -r .

-family xce4000x -mode all
XIL2CDS creates a body for the FPGA/CPLD called my_design_r_1.
Contact Cadence to obtain the XIL2CDS program and additional details on its operation.

Pin Locking
You may place the PADs on specific pins of your target device by adding the “LOC” property to the IBUF or OBUF that connects to it. If you use a “bussed” I/O buffer symbol (for example, IBUF8), you must add the pin constraints to the UCF file instead. 
NOTE
You cannot put the LOC property on the PAD or the net between the PAD and I/O buffer. If you do, it will be ignored since Concept does not support properties on pads.
To add a LOC property:

Enter the “Attribute” mode, and select the IBUF/OBUF you wish to constrain.


Select Add, and enter LOC in the Name field, and the pin name in the Value field. 

Valid pin syntax for the quad flat packages is P#, where # is the actual device pin number desired. For example: LOC=P11.

Valid pin syntax for the grid array packages (BGA, PGA) is RC, where R is the actual row and C is the actual column of the device pin.


Select Done. You may re-position the LOC property above the PAD, using the Move command in Concept.




Timing Constraints
Timing constraints may be placed as properties on a TIMESPEC symbol in the design. Click on the “Attribute” button in Concept, then select the TIMESPEC symbol to display the list of properties. Select “Add” to add a new property. The Timespec label (the label that begins with “TS”) is entered in the Name field, while the timing specification (for example, “FROM:FFS:TO:FFS=30ns”) is entered in the Value field. By default, you may only use “TS” labels “TS01” through “TS10” with Concept. If you wish to use other labels, you must copy the $XILINX/cadence/data/xilinx.pff file to your design directory, and add entries for other labels. For more information on this subject, refer to the Cadence Interface/Tutorial Guide. For more information on timing constraints, see the Development System Reference Guide.