This appendix provides information on installing and using the Alliance FPGA Express and the Xilinx Alliance Series release. Synopsys and the Xilinx CD-ROM documentation are referenced to help you find additional information. The Alliance FPGA Express is FPGA Express software purchased from Synopsys. Foundation Express is the FPGA Express software bundled with the current release of the Foundation Express and is purchased from Xilinx. All references to FPGA Express in this appendix refer to Alliance FPGA Express. For more information on Foundation Express, refer to the Foundation Series Quick Start Guide 1.5.
FPGA Express is a Verilog/VHDL compiler designed to work with Windows 95 and Windows NT v4.0. FPGA Express can process either Verilog or VHDL files. FPGA Express writes out XNF that is fully compatible with Alliance Series Design Implementation tools. Only the implementation tools and a third party simulation tool are needed in addition to FPGA Express to fully create and simulate a design. This appendix includes the following sections.
The following documentation is available for FPGA Express and the Alliance Series Design Implementation tools for the current release of software.
FPGA Express is the top-level design tool in the design flow. FPGA Express writes out an XNF file that is fully compatible with the Alliance Series Design Implementation tools. The XNF file written out by FPGA Express can be accepted by NGDBuild or the Design Manager for creation of a PROM file.
The following types of simulation are possible with FPGA Express.
For more specific information on simulation with FPGA Express, refer the FPGA Express Design Guide.
Refer to the following figure for a graphic representation of the design flow.
Figure B.1 Alliance FPGA Express/Xilinx Design Flow |  |
Insert the FPGA Express CD into your CD-ROM drive. Start the Explorer and double-click on the CD-ROM icon. Double-click on setup.exe to start the install process.
For additional instructions on how to install FPGA Express on Windows 95 or Windows NT, refer to the FPGA Express User's Guide included with the FPGA Express software from Synopsys.
To enter a design, use the following steps.
Synopsys FPGA Express New... Identify Sources Create Implementation Optimize Chip Export NetlistVerilog or VHDL designs are the input files for the FPGA Express design flow, and the output is an XNF file, which can be processed directly by the Xilinx implementation tools. For details on defining projects in FPGA Express, entering HDL code, defining constraints in FPGA Express, supported devices, and design issues, refer to the FPGA Express User's Guide included with your FPGA Express software from Synopsys.
FPGA Express synthesizes your designs based on die size. If necessary, FPGA Express can wrap carry logic from one column to the next. You should use the device that is targeted for synthesis by FPGA Express as the target device for the Xilinx place and route tools.
FPGA Express is a synthesis tool only. Simulation of designs with FPGA Express must be done with a third party simulation tool. For more information on simulation with FPGA Express, refer to the documentation of your third party simulation tool.
For VHDL simulation, the Xilinx VITAL libraries are required. The Xilinx VITAL libraries are located in the $XILINX/vhdl directory, ($XILINX is where the Xilinx software is installed). For Verilog simulation, the Xilinx Verilog libraries are required. The Xilinx Verilog libraries are located in the $XILINX/verilog directory.
For more information on the HDL simulation flow with FPGA Express, refer the Development System Reference Guide. For a general overview of Xilinx simulation, refer the Development System User Guide. For information on using the Design Manager in HDL simulation, the Design Manager/Flow Engine Reference/User Guide.
There are three types of simulation possible behavioral, post-NGDBuild, and back-annotated timing simulation.
FPGA Express automatically inserts timespecs into the XNF file it writes out. Optionally, the user can choose not to write out timespecs in the XNF file from FPGA Express. Instead, you can write the constraints in a .ucf file. The timespecs created by FPGA Express in the XNF file have the FROM: TO syntax.
For more information on constraints and FPGA Express, refer to the FPGA Express Expert Journal at (http://www.xilinx.com).
Read this section if you are porting a design from FPGA/Design Compiler to FPGA Express. If you are compiling a design originally compiled with FPGA/Design Compiler and the code is one hundred percent behavioral, then no modification of the code is needed. But, if you have instantiated components from the XSI libraries, some of these components do not exist in the FPGA Express libraries.
Some of the components that can be instantiated in the Xilinx design flow cannot be instantiated in the FPGA Express tool, since there are slight differences in names. For example, the BUFGP_F in the XSI component library does not exist in the FPGA Express component library. In FPGA Express, the equivalent name of the BUFGP_F is BUFGP. For a complete listing of the library cells that can be instantiated in FPGA Express, refer to the contents of the following.
fpgaexpress/lib/xc3000fpgaexpress/lib/xc4000efpgaexpress/libxc5200The fpgaexpress directory is where FPGA Express is installed on your system. In these directories, there are files with a .dsn extension. The string in front of .dsn is the name of the CELL that can be instantiated in FPGA Express.
In general, instantiation is not necessary. For the XC4000EX/XL/XLA/XV FPGA Express flow, you must instantiate the following components.
For examples of instantiation of I/O muxes, fast capture latches, RAM, and BSCAN, refer to the “Synopsys (XSI) Interface Notes” appendix.
For information on using LogiBLOX and FPGA Express, refer to the FPGA Express Expert Journal at (http://www.xilinx.com).
