Appendix G

Instantiated Components

This appendix lists the components most frequently instantiated in synthesis designs. The function of each component is briefly described and the pin names are supplied, along with a listing of the Xilinx product families involved. For a complete list of components, see the online version of the Libraries Guide, Synopsys (XSI) Interface/Tutorial Guide, or your synthesis tool documentation. This chapter contains the following sections.

• “STARTUP Component”
  
  
• “STARTBUF Component”
  
  
• “BSCAN Component”
  
  
• “READBACK Component”
  
  
• “RAM and ROM”
  
  
• “Global Buffers”
  
  
• “Fast Output Primitives”
  
  
• “IOB Components”
  
  
• “Clock Delay Components”
  
  

STARTUP Component

The STARTUP component is used to access the global set/reset and global tristate signals. STARTUP can also be used to access the start-up sequence clock. For information on the start-up sequence and the associated signals, see The Programmable Logic Data Book and the Xilinx Libraries Guide.

The STARTUP component cannot be simulated. For Verilog GTS/GSR simulation see the Cadence Interface/Tutorial Guide. For VHDL designs, use components in the following table and refer to the Development System User Guide for HDL simulation information.

Table G_1 STARTUP Library Component

STARTBUF Component

The STARTBUF component allows you to functionally simulate the STARTUP component. As with STARTUP, a STARTBUF component instantiated in your design specifies to the implementation tools to use GSR. Using the STARTBUF component in VHDL designs is the preferred method for using GSR/GR.

Table G_2 STARTBUF Library Component

BSCAN Component

To use the boundary-scan (BSCAN) circuitry in a Xilinx FPGA, the BSCAN component must be present in the input design. The TDI, TDO, TMS, and TCK components are typically used to access the reserved boundary-scan device pads for use with the BSCAN component but can be connected to user logic as well. For more information on the BSCAN component, the internal boundary-scan circuitry, and the directional properties of the four reserved boundary-scan pads, refer to Programmable Logic Data Book and the online version of the Xilinx Libraries Guide.

Table G_3 BSCAN Library Components

READBACK Component

To use the dedicated readback logic in a Xilinx FPGA the READBACK component must be inserted in the input design. The MD0, MD1, and MD2 components are typically used to access the mode pins for use with the readback logic, but can be connected to user logic as well. For more information on the READBACK component, the internal readback logic, and the directional properties of the three reserved mode pins, see the Programmable Logic Data Book and the online manual Libraries Guide.

Table G_4 Readback Library Components

RAM and ROM

Some of the most frequently instantiated library components are the RAM and ROM primitives. Because most synthesis tools are unable to infer RAM or ROM components from the source HDL, the primitives must be used to build up more complex structures. The following list of RAM and ROM components (Table G-4) is a complete list of the primitives available in the Xilinx library. For more information on the components, see the Programmable Logic Data Book and the online manual Libraries Guide.

Table G_5 RAM and ROM Library Components

Global Buffers

Each XC4000EX and XC4000XL device has 16 available global buffers: 8 BUFGLSs and 8 BUFEs. For some designs it may be necessary to use the exact buffer desired to ensure appropriate clock distribution delay. For most designs, the BUFG, BUFGS, and BUFGP components can be inferred or instantiated, thus allowing the Alliance Series Design Implementation Tools to make an appropriate physical buffer allocation. For more information on the components, see the Programmable Logic Data Book.

Table G_6 Global Buffers Library Components

Fast Output Primitives

One of the features added to the XC4000EX and XC4000XL architectures is the fast output MUX. There is one fast output MUX located in each IOB which can be used to multiplex between two signals on a single device pad or can be used to implement any two input logic function. Each component can have zero, one, or two inverted inputs. Because the output MUX is located in the IOB, it must be connected to the input pin of either an OBUF or an OBUT. For more information on the output primitives, see the Programmable Logic Data Book. For information on how to instantiate output MUXs with inverted inputs, see the Synopsys (XSI) Interface/Tutorial Guide.

Table G_7 Fast Output Primitives

IOB Components

Depending on the synthesis vendor being used, some IOB components must be instantiated directly in the input design. Most synthesis tools support IOB D-type flip-flop inferences, but may not yet support IOB D-type flip-flop inference with clock enables. Because there are many slew rates and delay types available, there are many derivatives of the primitives shown. For a complete list of the IOB primitives, see the Synopsys (XSI) Interface/Tutorial Guide.

Table G_8 IOB Components

Clock Delay Components

These components are delay locked loops that are used to eliminate the clock delay inside the device. The delay locked loop is a digital variation of the analog phase locked loop.

Table G_9 Clock Delay Component