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Appendix F

Using LogiBLOX with CAE Interfaces

LogiBLOX is graphical design tool for creating high-level modules such as counters, shift registers and multiplexers. LogiBLOX includes both a library of generic modules and a set of tools for customizing these modules.

With LogiBLOX, high-level LogiBLOX modules that will fit into your schematic-based design, or HDL synthesis-based design can be created and processed. These modules can be used in designs generated with schematic editors from Mentor Graphics, Viewlogic and Xilinx Foundation Package, as well as third-party synthesis tools such as Synopsys FPGA Compiler/FPGA Express, and Exemplar.


NOTE

LogiBLOX supports XC3000A, XC3100A, XC4000E, XC4000L, XC4000EX, XC4000XL, XC4000XV, XC4000XLA, XC5200, XC9500, XC9500XL, Spartan, and Spartan XL.


This chapter includes the following sections.

Documentation

The following documentation is available for the LogiBLOX program.

Setting Up LogiBLOX on a Workstation

This section describes the issuing commands and the file modifications required to set up your environment when using a third-party schematic design tool on a workstation. You must set up the Xilinx environment and interface environment as described in the “Installing the Software” chapter and in the appropriate appendix in this manual.

Mentor Interface Environment Variables

To use LogiBLOX with Mentor, set the following environment variable.

setenv LCA $XILINX/mentor/data
setenv SIMPRIMS $LCA/simprims

Also verify that your $MGC_LOCATION_MAP file contains the following entries.

$LCA
(blank)
$SIMPRIMS
(blank)

Synopsys Interface Environment Variables

To use LogiBLOX with Synopsys, add the following entries to the .synopsys_vss. setup file, located in the working directory.

logiblox:
$XILINX/synopsys/libraries/sim/logiblox/lib

Viewlogic Interface Environment Variables

To use LogiBLOX with Viewlogic, add the following path to the WDIR environment variable.

${XILINX}/viewlog/data/logiblox/standard\

The following is an example.

setenv WDIR ${XILINX}/viewlog/data/logiblox/standard:<existing-WDIR>

Verify that the following two libraries have been added to the search order in the local viewdraw.ini file right before the “builtin” and “xbuiltin” libraries. Modify the file with the following entries.

DIR [r]/xilinx_path/viewlog/data/logiblox (logiblox)
DIR [m]/xilinx_path/viewlog/data/simprims (simprims)

Setting Up LogiBLOX on a PC

This section describes the issuing commands and the file modifications required to set up your environment when using a third-party schematic design tool on a PC. You must set up the Xilinx environment and interface environment described in the “Installing the Software” chapter manual and in the appropriate appendix in this manual.

Viewlogic Interface Environment Variables

To use LogiBLOX with Workview Office, run the following command in an MS-DOS session.

custmenu xilinx_path\viewlog\data\viewblox.txt

Verify the following two libraries are included in the search order in the Viewlogic Project Manager right before the “builtin” and “xbuiltin” libraries.

[r] <xilinx_path>\viewlog\data\logiblox (logiblox)
[m] <xilinx_path\viewlog\data\simprims (simprims)

Starting LogiBLOX

LogiBLOX can be started in one of three ways.

Using LogiBLOX for Schematic Design

LogiBLOX modules can be created for use in schematic designs using third-party design tools. First, the module must be created. The module can then be added to the schematic like any other library component with the aid of the LogiBLOX GUI.

Creating a LogiBLOX Module

To create a LogiBLOX module, follow these steps.

  1. From ViewDraw or Mentor Graphics, select the appropriate menu choice in your design tool to start LogiBLOX. The LogiBLOX Module Selector dialog box appears.

  2. Select a base module type (for example, Counter, Memory).

  3. Customize the module by selecting pins and specifying attributes.

  4. Click OK.

LogiBLOX generates a schematic symbol and a simulation model for the module you have selected.


NOTE

You can add existing LogiBLOX components from the project library.


Design Simulation

You can functionally simulate your design at any time.

At this point the design is ready to be processed for both simulation and implementation. Because LogiBLOX creates a component with a VHDL or EDIF simulation model describing its behavior, the simulation and implementation flow for a design containing LogiBLOX components is no different than for a design which does not contain LogiBLOX components. Once created, the LogiBLOX components can be used repeatedly in any design.

Copying Modules

If you copy a module within your schematic or add repeated instances, the original module and all of its copies share the same .mod file and simulation model. Subsequent modifications to any one of these modules changes all copies of that module. If you copy a module from another design, such as by copying an entire hierarchical module, you must invoke the LogiBLOX program and cause it to regenerate the module and re-create the simulation model for that module. Alternatively, if your design includes several copied modules, you can copy the raw HDL files into the new project directory and re-analyze them in the new environment.

Using LogiBLOX for HDL Synthesis Design

LogiBLOX modules can be instantiated in HDL designs to address special features, such as distributed memory (XC4000E and XC4000EX), special I/O configurations, and other advanced silicon features that cannot be inferred by the HDL synthesizer.

The LogiBLOX program creates a simulation netlist (VHDL, EDIF or Verilog), an implementation netlist file (.ngc), and a template file containing a VHDL (.vhi) or Verilog (.vei) component instantiation.

Instantiating a LogiBLOX Module

To instantiate a LogiBLOX module, proceed with the following steps.

  1. Start LogiBLOX from the command line, or click on the LogiBLOX icon. See the “Starting LogiBLOX” section.

  2. Select Setup on the Module Selector dialog box. The Setup dialog box appears.

  3. The Setup dialog window displays initially if a logiblox.ini file is not found in the home directory.

  4. Select Options. The Options selections appear.

  5. Select the Simulation model you require (VHDL, EDIF, or Verilog).

  6. Click OK. The Setup dialog box disappears.

  7. Create the module you want in the LogiBLOX Module Selector dialog box.

  8. Click OK.

  9. Instantiate the module in the top level.

    With a text editor, cut and paste the contents of the VHDL (.vhi) or verilog (.vei) design file to the top level design. Then, specify the design names in the component instantiation section.

Analyzing a LogiBLOX Module

Before starting behavioral simulation on an instantiated LogiBLOX module, the LogiBLOX library has to be analyzed. The following three sections list the commands that can be used in Mentor, Synopsys, and Viewlogic to analyze the library.

Mentor QuickHDL

Enter the following series of commands from your workstation command line to analyze the LogiBLOX libraries.

$XILINX/mentor/data/vhdl/compile_vhdl_libs.sh
(VHDL)

$XILINX/mentor/data/verilog/compile_verilog_libs.sh (Verilog)

See the accompanying README files in the same directories for more information on these scripts.

Synopsys VSS

Enter the following series of commands from your workstation command line to analyze the LogiBLOX libraries.

$XILINX/synopsys/libraries/sim/src/logiblox/analyze.csh

The script analyzes the model and places the output files in the $XILINX/synopsys/libraries/sim/lib/logiblox directory.

Viewlogic Vantage

Enter the following command from your workstation/PC command line to analyze the LogiBLOX libraries.

vaninit parent_directory

This is a script provided by Xilinx. The new logiblox.lib Vantage library directory will be created under the specified parent_directory. You do not need to re-analyze the LogiBLOX library for every new project.

MTI Modelsim

Enter the following command from your workstation/PC command line to analyze the LogiBLOX libraries.

VHDL Designs

vlib /destination/path /simprim

vmap simprim /destination/path /simprim

vcom -work simprim $XILINX/vhdl/src/simprims/simprim_Vpackage.vhd

vcom -work simprim $XILINX/vhdl/src/simprims/simprim_Vcomponents.vhd

vcom -work simprim $XILINX/vhdl/src/simprims/simprim_VITAL.vhd

Verilog Designs

vlib /destination/path /simprim

vmap simprim /destination/path /simprim

vlog -work simprim $XILINX/verilog/src/*.vmd

LogiBLOX Modules

LogiBLOX has many different modules that you can use in a schematic or HDL synthesis design. The following is a list of the LogiBLOX modules.

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