Step 7: Evaluating Post-Layout Timing

After the design is placed and routed, you can generate the Post-Layout Timing Report to verify that the design meets the desired timing goals. This report evaluates both the logical block delays as well as the routing delays. The net delays are now reported as actual routing delays after the place and route process.

Because the option to produce a Post-Layout Timing Report was previously selected, you can proceed with the Timing stage of the design process.

1. From within the Flow Engine, select the following to run only the Timing phase.
   
   Flow Step
   
   
2. Once completed, select the following.
   
   Utilities Report Browser
   
   Open the newly created Post-Layout Timing Report. At this point, the minimum period for the design is 7.121ns, still well within the timing constraint of 20ns.
   
   
3. To obtain a more detailed analysis of post-layout timing, select the following from the Design Manager to start the Timing Analyzer tool.
   
   Tools Timing Analyzer
   
   The Timing Analyzer performs static timing analysis on designs that are mapped and partially or completely placed, routed or both. It organizes and displays data so you can analyze critical paths in your circuit, circuit cycle times, delays on specified paths, and paths with the greatest delay.
   
   In this tutorial, the Timing Analyzer automatically loads the placed and routed netlist as well as a physical constraints file. The PCF file contains the same constraints specified in the UCF file, however now expressed in terms of physical elements.
   
   
4. Select the following.
   
   Analyze Timing Constraints Report Paths in Timing Constraints
   
   The Timing Analysis In Progress dialog box is displayed while a verbose report is generated. Once complete, the report automatically appears in the Timing Analyzer.
   
   After the Map process, logic delay contributed to 5.32 ns of the minimum period attained. The analysis report indicates that this value has not changed. However, the total unplaced floors estimate of 1.032 ns has changed. The routing delay after PAR equals 1.801 ns (2 x .23 + .236 + 1.105). This is now a true report of net delays after the place and route stage.
   
   The post-layout result does not necessarily follow the 50/50 rule described previously because the worst case path is made up of mainly component delays. After mapping the design, block delays constituted about 80% of the period. Following place and route, the worst case path is still almost 75% logic delay. Since there is only 1.801ns of total routing delay spread out across four nets, expecting this to be reduced any further is not reasonable, especially considering that routing delay only makes up 25% of the total path delay.
   
   Because the timing requirements are not overly aggressive for this design, no timing errors are generated. If a design failed to meet a timespec, one solution is to reduce logic levels in order to reduce block delays.
   
   
5. Select the following to close the Timing Analyzer.
   
   File Exit
   
   At this point, you can either save the generated report or discard the results. For information on using more advanced features in the Timing Analyzer, refer to the Timing Analyzer Reference/User Guide.