Step 8: Creating Timing Simulation Data

With the design placed and routed and the timing statically verified, the next step is to create timing simulation data for the design. The Modelsim VHDL is selected for the simulator. VHDL is targeted as the back-annotated format for the simulation data.

1. To create VHDL format simulation data, perform the following steps in the Flow Engine.
   
   
   1. Select Setup Options to open the Options dialog box.
      
      
   2. Select Modelsim VHDL from the Simulation Option Template pull-down menu.
      
      
   3. Click on the Produce Timing Simulation Data option.
      
      
   4. Click OK to close the Options dialog box.
      
      
2. Select Flow Step Back from the Flow Engine menu to backup to the Place & Route Completed stage.
   
   
3. Select Flow Step to run Timing.
   
   

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   NOTE

   The Timing phase of the Flow Engine produces timing simulation data. This stage is necessary because the option to produce timing simulation data was not selected in the initial pass.

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   During Timing, the Flow Engine runs the NGDAnno program to create a back-annotated NGD file. The NGD file is then used as the input to one of the NGD2XXX programs to produce the preferred simulation file format. Because Modelsim VHDL was specified, the Flow Engine runs NGD2VHDL and creates, by default, the files tim_sim.vhd and tim_sim.sdf. The first file is a structural VHDL file and the second is a Standard Delay Format file. To make it easy to find these files to use in a third party simulation environment, they are automatically copied to the working directory.