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Appendix B

Targeting Virtex Devices

Generally, you target a Virtex device no differently than the way you target a non-Virtex device. However, you use Virtex-specific settings, such as .synopsys_dc.setup options, that only apply to Virtex. This appendix outlines only the major differences you encounter when targeting a Virtex device. For topics not covered here, equivalent instructions for a non-Virtex device apply and those instructions exist earlier in this manual.

Unless otherwise specified, all references to FPGA Compiler also apply to Design Compiler.

This appendix contains the following topics.

Following General Guidelines

Use these following general guidelines when targeting Virtex devices.

Virtex XSI uses an EDIF-based synthesis flow with FPGA Compiler and FPGA Express.

“XSI Library Primitives”

For I/O cells with a specific type of input delay, and current drive in the FPGA Compiler flow, instantiate the desired IBUF, OBUF, IFD, and other primitives. Refer to the Appendix for the exact I/O library cell name and pin names. For I/O cells in FPGA Express, you can infer the desired type of input delay, pull-up or pull-down, and current drive using the FPGA Express implementation GUI.

Do not use the Ungroup -all -flatten command when synthesizing a Virtex design with FPGA Compiler.

A software bug exists in the DesignWare Compiler and the uniquify command can build incorrect operators in a module uniquified before the operator expanded to Virtex components. Compile all modules with operators in them prior to running the uniquify command. Do not set the Synopsys variable hdlin_replace_synthetic=true to expand the operators while reading in the HDL design code. Doing so can result in less-than-optimal designs because the compiler cannot make appropriate trade-offs.

Compile designs with hierarchy that include a twice-used module before running the uniquify command. Use the following commands for such a design, selecting the appropriate level (low, medium, or high).

current_design alu compile -map_effort \
[low|medium|high]

current_design top uniquify compile -map_effort \
[low|medium|high]

You can use two types of simulation when simulating a Virtex design with either Verilog or VHDL, RTL simulation and post-NGDbuild simulation.

Setting FPGA Compiler to Synthesize a Virtex Design

Use the following procedure to set FPGA Compiler for Virtex design simulation.

  1. Set your Xilinx and Synopsys software environments.

    For instructions about setting up this current release of Xilinx software, please refer to the A1.5 Install Guide. For instructions about setting up Synopsys products, refer to the Synopsys installation guide.

  2. Copy the file $XILINX/synopsys/examples/template.synopsys_dc.setup_fc into a directory.

  3. Run synlibs to get the correct synthesis libraries into the .synopsys_dc.setup file. Execute the following command in the same directory that contains the .synopsys_dc.setup file for Virtex.

    synlibs xfpga_virtex-3>>.synopsys_dc.setup

  4. Check that your system administrator compiled the XDW A1.5 XSI libraries.

    By default, these DesignWare libraries are compiled for Synopsys v1997.01. If using a version of Synopsys newer than v1997.01, compiler these libraries for the version of Synopsys you use. Check with your system administrator to determine the version of Synopsys installed and in use.

  5. Determine if you need to compile the A1.5 XDW libraries for Virtex and have privileges to write to $XILINX.

    If you do not have privileges to write in $XILINX, copy the contents of $XILINX/synopsys/libraries to a local directory and then follow steps 2-4, except use the following procedures in the local copy of $XILINX/synopsys/libraries.

    1. Change directories to the $XILINX/synopsys/libraries/dw/src/virtex area.

    2. Inside the previous directory, type the following and press Enter.

      dc_shell -f install_dw.dc

      To synthesize the Virtex A1.5 XSI XDW Virtex libraries you must have a license to compile VHDL with Synopsys. If you do not have a VHDL license, check the Xilinx WWW site (www.xilinx.com) for a compiled version of the XSI XDW Virtex A1.5 XDW libraries.

    3. Compile the XSI XDW A1.5 libraries only once. You need to recompile only when upgrading to a new version of Synopsys.

Synthesizing a Virtex Design into FPGA Compiler

Use the following procedure to synthesize a Virtex design into FPGA Compiler.

  1. Set up the .synopsys_dc.setup file.

  2. Synthesize the A1.5 XDW libraries.

  3. Create a WORK directory in the same directory that contains the .synopsys_dc.setup file.

  4. Create the run script, as shown in the following example.

    /*Basic Virtex FPGA Compiler Compile script */

    read -f verilog file1.v
    read -f verilog file2.v
    read -f verilog file3.v
    . . .
    read -f verilog top.v

    /* Set design constraints */
    /* Use the following commands if you want */
    /* Synopsys to infer I/O. It is recommended */
    /* for the Virtex flow that I/O be */
    /* instantiated. */
    /* set_port_is_pad “*” */
    /* set_pad_type -no_clock all_inputs() */
    /* set_pad_type -exact BUFGP -clock \ */
    /* find(port,”CLK”) */
    /* insert_pads */

    compile

    /* Use analysis reports to evaluate quality */
    /* of results. */
    /* report_area */
    /* report_timing */

    write_script > design.dc
    sh dc2ncf -w design.dc

    write -hierarchy -format db -o “top.db”
    write -hierarchy -format edif -o “top.edif”

Setting VSS Simulation for Virtex

Use the following procedure to set VSS simulation for Virtex devices.

NOTE

To compile the simulation libraries, you must have root access because you modify files in the $XILINX tree. As with the XDW libraries, you must compile these libraries if using a version of Synopsys newer than v1997.01. If you need to compile these libraries, you must have write privileges to the $XILINX area. If you do not, copy the $XILINX/synopsys/libraries/sim to a local directory.

  1. Change to the $XILINX/synopsys/libraries/sim/src/unisims directory.

  2. In the previous directory, run the C-shell script analyze.csh.

  3. Change to the $XILINX/synopsys/libraries/sim./src/simprims directory.

  4. In the previous directory, run the C-shell script analyze.csh.

    You need do the previous three steps only once. However, if you upgrade to a new version of Synopsys, you must recompile these libraries again.

    If simulating in Verilog, ignore the previous three steps.

  5. Copy the file $XILINX/synopsys/examples/template.synopsys_vss.setup file into a directory where you perform VSS simulation.

  6. Rename the file template.synopsys_vss.setup to .synopsys_vss.setup.

  7. Create a WORK directory.

    You can now start simulating with VSS.

Setting FPGA Express for Virtex

Use FPGA Express v2.1 or later to synthesize a Virtex design. When creating an implementation in FPGA Express, select Virtex as a family/die-pkg-spd grade. For more information on FPGA Express, refer to the F1.5 Foundation Express documentation, or the Alliance FPGA Express documentation which comes with your FPGA Express software from Synopsys.

Figure B.1 Virtex Implementation Window

Synthesizing a Virtex Design in FPGA Express

The design procedure you use to target a Virtex device with FPGA Express mimics the procedure for targeting a XC3000A/XC4000X/Spartan device with FPGA Express. For more information on FPGA Express, refer to the F1.5 Foundation Express documentation, or the Alliance FPGA Express documentation which comes with your FPGA Express software from Synopsys.

Using Clock Delay Locked Loops with Synopsys

You can simulate and implement the clock delay loops DLLs CLKDLL and CLKDLLHF in HDL code. To use these DLLs for synthesis, change the following two types of attributes.

To changes these default values in FPGA Compiler, use the Set Attribute command. To change the value of DUTY_CYCLE_CORRECTION and CLKDV_DIVIDE, you must know the instance name of the instantiated CLKDLL/CLKDLLHF. For example, if you have instantiated the CLKDLL in your top-level VHDL file, the VHDL code can appear as the following.

MYDLL: CLKDLL port map(CLKIN=>REFCLK,CLKFB=>signal1,.);

In Verilog, the code can appear as follows.

CLKDLL MYDLL (.CLKIN(REFCLK), .CLKFB(signal1),.);

In both cases, the instance name is CLKDLL. To change the values of DUTY_CYCLE_CORRECTION and CLKDV_DIVIDE, use the Set Attribute command in the run script. Use the Set Attribute command before writing out the EDIF file from FPGA Compiler, as shown in the following example.

set_attribute “MYDLL” “DUTY_CYCLE_CORRECTION”\
-type string “FALSE”
set_attribute “MYDLL” \
“CLKDV_DIVIDE “ -type string “3.0”

To change the defaults of CLKDLL and CLKDLLHF in FPGA Express, use the constraints GUI in FPGA Express.

To simulate CLKDLL and CLKDLLHF with Verilog, use the functional simulation model that exists in the UNISIM libraries included in the A1.5 software. If you changed the default values of DUTY_CYCLE_CORRECTION and CLKDV_DIVIDE, specify these changes in the functional simulation by using a `define macro to override the DUTY_CYCLE_CORRECTION and CLKDV_DIVIDE parameters.

To simulate CLKDLL and CLKDLLHF with VHDL, use the functional simulation model that exists in the UNISIM libraries included in the A1.5 XSI software. If you changed the default values of DUTY_CYCLE_CORRECTIO and CLKDV_DIVIDE, specify these changes in the functional simulation by using generics when instantiating the CLKDLL/CLKDLLHF.

NOTE

Generics for DUTY_CYCLE_CORRECTIOIN and CLKDLLHF do not allow you to change the default values for synthesis. Use the Set Attribute command to do this, or the GUI of FPGA Express.

The following example shows how to use generics to change the default values of the CLKDLL for functional VHDL simulation.

MYDLL: CLKDLL generic map(DUTY_CYCLE_CORRECTION=>FALSE, \
CLKDV_DIVIDE=>3.0) port map(CLKIN=>..);

For more information about CLKDLL and CLKDLLHF, please refer to the Databook or the Libraries Guide.