Appendix A

XSI Library Primitives

You can find the XSI primitives in the XSI-supplied libraries in FPGA Compiler and FPGA Express; you can instantiate them in your VHDL or Verilog HDL file. Use the synlibs program to list the appropriate libraries for a specific part type. Refer to the “Getting Started” chapter for information on how to use synlibs.

In the primitive tables in this appendix, the names of the inputs and outputs follow the primitive names, the applicable architecture, and any important notes. All primitives in the libraries contain timing parameters. The Notes column includes specific timing details and additional functional information.

Although Synopsys cannot synthesize some primitives (primitives with the Dont Touch and Dont Use attributes), you can instantiate them. An asterisk (*) next to the primitive name indicates that you can instantiate it. Refer to the Synopsys documentation for more information on the Dont Touch and Dont Use attributes. Use the name of a primitive to instantiate it. In addition, you must identify the signals connected to the input and output pins when instantiating a primitive.

In general, pins are organized with data pins before control pins. When several pins are part of a bus, they are listed with the MSB first. Buses of four or more bits follow bus notation, for example, A<7:0>. Buses with fewer bits are kept as separate signals.

The following sections are included in this appendix.

• “Generating a List of XSI Library Primitives” section
  
  
• “Obtaining XSI Library Primitive Pin Order” section
  
  
• “Alphabetical List of Primitives for All Architectures” section
  
  
• “Understanding Virtex-Specific Cell Names” section
  
  
• “Xilinx DesignWare Modules” section
  
  
• “Post-Configuration Initialization States” section
  
  

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  NOTE

  Synopsys FPGA Express does not recognize the underscore character (“_”) as valid.

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Generating a List of XSI Library Primitives

You can use the following procedure to generate a list of the XSI library primitives provided in this appendix.

1. Start DC Shell or Design Analyzer in a directory that contains your .synopsys_dc.setup file. Ensure this setup file points to the libraries you need to synthesize your designs in the XSI design flow.
   
   
2. In the command window of Design Analyzer or in DC Shell, enter the following command.
   
   read -f db link_library
   
   
3. In the command window of Design Analyzer or in DC Shell, enter the following command.
   
   list -files
   
   This command lists all the library files in memory.
   
   
4. For each item in the list, enter the following command.
   
   find cell filename/*
   
   filename is the .db library file.
   
   For example, for the library file xfpga_4000e-3.db the Find Cell command lists the following.
   
   xfpga_4000e-3/clb_4000

xfpga_4000e-3/iob_4000
   
   

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   NOTE

   The library file lists first, followed by the library primitive.

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Obtaining XSI Library Primitive Pin Order

Positional notation allows you to instantiate a primitive without explicitly specifying the pins for that component. To use this notation, you must know the pin order of the primitive. You can use the following procedure to obtain the pin order for any of the XSI library primitives provided in this appendix.

1. Start DC Shell or Design Analyzer in a directory that contains your .synopsys_dc.setup file.
   
   
2. In DC Shell or in the command window of Design Analyzer, enter the following command.
   
   read -f db link_library
   
   
3. In DC Shell or in the command window of Design Analyzer, enter the following command.
   
   list -files
   
   This command lists all the library files in memory. Know which file contains the relevant primitive.
   
   
4. In DC Shell or in the command window of Design Analyzer, enter the following command.
   
   find (pin, “dbfilename/cellname/*”)
   
   dbfilename is the name of the .db file that contains the primitive and cellname is the relevant primitive.
   
   For example, the following command finds the pin order of the OR2 primitive in the XC4000EX library.
   
   find (pin, “xprim_4000ex-3/OR2/*”)
   
   This results in the following pin order.
   
   {“O” “I1” “I0”}
   
   

Alphabetical List of Primitives for All Architectures

This section lists the XSI primitives in alphabetical order with their associated output, input, and bidirectional pins. In addition, the pins are listed in the order used for positional notation. For example, the pins for ACLK are listed with the O pin first, followed by the I pin. Therefore, you can instantiate ACLK with only the signal (wire) names; you do not need to declare the ACLK pins. You can also find the applicable architecture and any notes in the tables included in this section.

Using the Dont Touch Attribute

An asterisk (*) next to a primitive name indicates that you must instantiate it. Also, you must apply the Dont Touch attribute to instantiated primitives. Refer to the Synopsys documentation for more information on the Dont Touch attribute.

Finding FPGA Express Primitives

Synopsys FPGA Express does not recognize the underscore character (“_”) as valid.

Primitive Name Suffixes

The following table lists the primitive name suffixes and their corresponding descriptions.

Table A_1 Primitive Name Suffixes

Virtex-Specific Primitive Name Suffixes

The following table lists the Virtex primitive name suffixes and their corresponding descriptions.

Table A_2 Virtex Primitive Name Suffixes

Architecture Abbreviations

This appendix uses the architecture abbreviations listed in the following table.

Table A_3 Architecture Abbreviations

Primitive Tables

The following tables describe the XSI primitives.

Table A_4 “A”

Table A_5 “B”

Table A_6 “C”

Table A_7 “D”

Table A_8 “F”

Table A_9 “G”

Table A_10 “H”

Table A_11 “I”

Table A_12 “L”

Table A_13 “M”

Table A_14 “N”

Table A_15 “O”

Table A_16 “P”

Table A_17 “R”

Table A_18 “S”

Table A_19 “T”

Table A_20 “V”

Table A_21 “W”

Table A_22 “X”

Understanding Virtex-Specific Cell Names

The following sections list Virtex-specific suffixes, primitives, and RAM cell names.

Virtex-Specific Primitives Table

The following table describes the Virtex-specific XSI primitives.

Table A_23 Virtex-Specific Primitives

Virtex RAM Primitive Name Suffixes

The following table lists the Virtex RAM primitive names and their corresponding descriptions.

Table A_24 Virtex-Specific RAM

Xilinx DesignWare Modules

The following figure illustrates the Xilinx DesignWare (XDW) module naming conventions. The example shows a comparator module and contains the four possible components used in naming the modules. Other module names do not necessarily contain all four components.

Figure A.1 XDW Module Naming Conventions

The following table gives the XDW naming conventions.

Table A_25 XDW Naming Conventions

The following table maps XDW modules to X-BLOX Modules and provides inputs and outputs.

Table A_26 XDW Modules

Post-Configuration Initialization States

The following tables show the initialization states after configuration for the XC4000 and XC5200 families.

Table A_27 Initialization State After Configuration (XC4000 Family)

Table A_28 Initialization State After Configuration (XC5200 Family)