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Using Constraint Files

With the design implementation tools, you can control the implementation of a design by entering constraints. There are two basic types of constraints that you can apply to a design: location constraints and timing constraints. Location constraints are used to control the mapping and positioning of the logic elements in the target device. The most common location constraints are pad constraints. They are used to lock the pins of the design to specific I/O locations so that the pin placement is consistent from revision to revision.

Timing constraints tell the software which paths are critical, and therefore, need closer placement and faster routing. Conversely, timing constraints also tell the software which paths are not critical and, therefore, do not need closer placement or faster routing. Both the placer and the router can be timing constraint driven.

Design, Netlist, and User Constraints

Constraints can be entered throughout the design entry and implementation processes. Constraints can be entered during the design entry phase by adding them to a schematic, specifying them to a synthesis tool, or listing them in a user constraint file. These three approaches differ in the following ways.

Using the Xilinx Constraints Editor

The Constraints Editor is a Graphical User Interface (GUI) that you can run after the Translate program to create new constraints in a UCF file. The Editor is accessible from the Start button (Start Programs Xilinx Foundation Series Accessories Constraints Editor).

The Constraints Editor interface consists of a main window, three tab windows and a number of dialog boxes. For more details, refer to the DynaText document, Constraints Editor User Guide.

You can also directly enter constraints into a UCF file without using the Xilinx Constraints Editor. See the next section for details.

Creating A User Constraint File

The user constraint file (.ucf) is a user-created ASCII file that holds timing and location constraints. It is read by NGDBuild during the translate process, and is combined with an EDIF or XNF netlist into an NGD file. If a UCF file exists with the same name as the top-level netlist, then it will automatically be read. Otherwise, specify a file for User Constraints in the Options dialog.

The following example shows how to lock I/Os to pin locations and how to write Timespec and Timegroup constraints.

Figure 3.11 Locking I/Os to Pin Locations

   # This is a UCF comment

   # The constraints below lock the I/O signals to pads.
  
   # The net name that connects to the pad is used to 
   # constrain the I/O.
 
   # The pin grid array packages use pin names like B3 or  
   # T1, instead of P<Pin Number>.

   # Lock the input pins 

   NET FRED LOC = P18; 
   NET JIM<0> LOC = P20; 
   NET JIM<1> LOC = P23; 
   NET JIM<2> LOC = P24; 
   NET JIM<3> LOC = P25; 
   NET JIM<4> LOC = P26; 
   NET JIM<5> LOC = P27; 
   NET JIM<6> LOC = P28; 
   NET JIM<7> LOC = P38; 
   
   # Lock the output pins
 
   NET NED LOC = P19; 
   NET HIERARCHY_BLOCK/<IT0> LOC = P44 
   NET HIERARCHY_BLOCK/<IT1> LOC = P45 
   NET HIERARCHY_BLOCK/<IT2> LOC = P46 
   NET HIERARCHY_BLOCK/<IT3> LOC = P47 
   NET HIERARCHY_BLOCK/<IT4> LOC = P48 
   NET HIERARCHY_BLOCK/<IT5> LOC = P49  
   NET HIERARCHY_BLOCK/<IT6> LOC = P50 
   NET HIERARCHY_BLOCK/<IT7> LOC = P462

For more information on constraint precedence, refer to the “Constraint Precedence” section of the “Foundation Constraints” appendix in the Foundation Series User Guide.

This example shows how to specify timing constraints.

Figure 3.12 Specifying Timing Constraints

   ---User Constraint File (UCF):
 
   # This is a comment
 
   # Period specifies minimum PERIOD of CLK net. Offset specifies that  
   # data on MAY can arrive up to 6 ns before the clock edge arrives on CLK.
 
   # NOTE: Period constraints do not apply to elements in output pads.
 
   NET CLK PERIOD = 20 ns ; 
   NET MAY OFFSET = IN : 6ns : before : CLK_PD ;
 
   # Groups all clocked loads of CLK2 into CLK2_LOADS timegroup  
   # Groups all clocked loads of VAL into VAL_LOADS
  
   # timegroup TNM # => Timegroup NaMe
 
   NET CLK2 TNM=CLK2_LOADS ; 
   NET VAL TNM=VAL_LOAD ;
 
   # Specifies worst case speed of path from IPAD to CLK2 # loads. Includes  
   # pad, buffer, and net delays. TS0l is a Timespec identifier; it can  
   # have names of the form TS<string>. PADS (CLK2_PD) is a Timegroup name  
   # specified inside of a Timespec.
 
   TIMESPEC TS01=FROM : PADS (CLK2_PD) : TO : CLK2_LOADS=15ns ;
  
   # Specifies the maximum frequency for all loads clocked by CLK2. 
   TIMESPEC TS02=FROM : CLK2_LOADS : TO : CLK2_LOADS=30Mhz;
 
   # Specifies the minimum delay on the path from Synchronous RAM to OFD.  
   # Includes clock-to-out delay, net delay, and setup time.
 
   TIMESPEC TS03=FROM : CLK2_LOADS : TO : VAL_LOAD+15000ps ;

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