The Xilinx Flow Engine is the graphical interface that performs the map, place, route, (fit for CPLDs) and bitstream generation phases of the design flow. Results of these implementations are made available in reports and may be accessed through the Reports tab in the Project Manager.
The Foundation Project Manager provides menu and pushbutton access to other Xilinx tools such as the Timing Analyzer, PROM File Formatter, and Floorplanner. You can access these tools through either the Tools menu in the Project Manager or directly from the Project Flowchart pushbuttons.
After you have created a new design or opened an existing design, you can start the implementation tools. To start these tools, click the Implementation phase button in the Project Flowchart area.
If your project is an HDL or state machine design, the design is first analyzed and updated. Then the Synthesis/Implementation dialog box displays. See the following figure.
Figure 3.4 Synthesis/Implementation Dialog Box |  |
If your project is a schematic design, the Implement Design dialog box displays.
Figure 3.5 Implement Design Dialog Box | |
To set up options and modify Program Option templates, select the Options button. The Design Manager/Flow Engine Reference/User Guide explains in detail how to modify these templates.
After you have completed the dialog box, the Flow Engine displays and runs the design through the implementation tools.
The Flow Engine interface prominently displays the status of each phase of the design, as shown in the following figures.
Figure 3.6 Flow Engine Shows All Design Segments Completed (FPGAs) | |
Figure 3.7 Flow Engine Shows All Design Segments Completed (CPLDs) | |
The Flow Engine's first step, Translate, merges all of the input netlists. This is accomplished by running NGDBuild. For a complete description of NGDBuild, refer to the “NGDBuild” chapter of the Development System Reference Guide.
The next step is the technology mapper. Map optimizes the gates and trims unused logic in the merged NGD netlist. This step also maps the design's logic resources; logic in the design is mapped to resources on the silicon, and a physical design rule check is performed. The mapping process is accomplished by running the MAP executable. For more information about MAP, refer to the “MAP - The Technology Mapper” chapter in the online DynaText manual, Development System Reference Guide.
After the design is mapped, the Flow Engine places and routes the design. In the place stage, all logic blocks, including the configurable
logic blocks (CLB) and input/output blocks (IOB) structures, are assigned to specific locations on the die.
If timing constraints have been placed on particular logic components, the placer tries to meet those constraints by moving the corresponding logic blocks closer together.
In the routing stage, the logic blocks are assigned specific interconnect elements on the die. If timing constraints have been placed on particular logic components, the router tries to meet those constraints by choosing a faster interconnect. The place and route (PAR) process is accomplished by running the PAR executable. For more information about PAR, refer to the “PAR - Place and Route” chapter in the online DynaText document, Development System Reference Guide.
The CPLD fitter implements designs for the XC9500 devices. The fitter outputs several files: fitting report (design_name.rpt), static timing report (design_name.tim), guide file (design_name.gyd, programming file (design_name.jed), and timing simulation database (design_name.nga).
For detailed information about implementing CPLD designs, refer to the Foundation online help (Help 
Foundation Help CPLD Design Techniques or Help Foundation Help CPLD Design Flows).
After place and route, the Flow Engine translates the physical implementation into a binary stream. The binary stream is used to program the FPGA. The binary stream is saved as a configuration file (.bit) using the BitGen executable. For more information about the BitGen executable, refer to the “BitGen” chapter in the online Dynatext document, Development System Reference Guide.
You can program an FPGA using the Hardware Debugger or JTAG Programmer to download a bitstream to configure a device. You can also use a bitstream as an input to the PROM File Formatter, which creates a specific configuration program for PROM use.
At the end of a successful CPLD implementation, a .jed programming file is created. The JTAG Programmer uses this file to configure XC9500/XL CPLD devices.
The reports provide information on logic trimming, logic optimization, timing constraint performance, and I/O pin assignment. To access the reports, select the Reports tab from Project Flow area of the Project Manager. Double click the Implementation Report Files icon to open the Report Browser. To open a particular report, double click its icon, as shown in the “Report Browser (FPGAs)” figure, below.
The translation report (.bld) contains warning and error messages from the three translation processes: conversion of the EDIF or XNF style netlist to the Xilinx NGD netlist format, timing specification checks, and logical design rule checks. The report lists the following:
Figure 3.8 Report Browser (FPGAs) | |
Figure 3.9 Report Browser (CPLDs) | |
The Map Report (.mrp) contains warning and error messages detailing logic optimization and problems in mapping logic to physical resources. The report lists the following information:
The Map Report can be very large. To find information, use key word searches. To quickly locate major sections, search for the string `---` , because each section heading is underlined with dashes.
The Place and Route Report (.par) contains the following information.
The Pad Report lists the design's pinout in three ways.
The Fitting Report (design_name.rpt) lists summary and detailed information about the logic and I/O pin resources used by the design, including the pinout, error and warning messages, and Boolean equations representing the implemented logic.
A timing summary report shows the calculated worst-case timing for the logic paths in your design.
Options specify how a design is optimized, mapped, placed, routed, and configured. Options are grouped into objects called implementation, simulation, and configuration templates. Each template defines an implementation, simulation or configuration approach. For example, one implementation style could be Quick Evaluation, while another could be Timing Constraint Driven.
Figure 3.10 Flow Engine Options Dialog Box | |
You can have multiple templates in a project. To access the options and templates,
The default options settings accommodate most implementations. For information on the options, select Help Help Topics from the Flow Engine menu.
