Static Timing Analysis

You can perform timing analysis at several stages in the implementation flow to estimate delays.

• A post-synthesis pre-implementation display can be created for HDL designs with the Express Time Tracker.
  
  
• A post-map timing report can be generated to evaluate the effects of logic delays on timing constraints, clock frequencies, and path delays.
  
  
• A post-place-and-route timing report that incorporates both block and routing delays can be generated as a final summary of the design's timing constraints, clock frequencies, and path delays.
  
  

Detailed timing constraint, clock, and path analysis for post-map or post-place-and-route implementations are done with the interactive Timing Analyzer tool.

NOTE

Static timing analysis may make the synthesis and implementation processes run slower.

Static Timing Analysis After Synthesis (HDL Only)

You can examine static timing results with the Express Time Tracker after synthesis and before implementation. You must have the Foundation Express product to access the Time Tracker and the Express Constraints Editor.

1. After you synthesize your design, right click the optimized structure from the Versions tab.
   
   
2. Select View Synthesis Results.
   
   
3. Select the Paths tab from the Time Tracker to view estimated delays.
   
   

Static Timing Analysis After Map (FPGAs Only)

Post-map timing reports can be very useful in evaluating timing performance. Although route delays are not accounted for, the logic delays can provide valuable information about the design.

If logic delays account for a significant portion (> 50%) of the total allowable delay of a path, the path may not be able to meet your timing requirements when routing delays are added. In fact, if the logic-only-delays exceed the total allowable delay for a path or constraint, the place-and-route process can be skipped altogether, since the routing delays will only cause the path's timing to degrade.

Routing delays typically account for 40% to 60% of the total path delays. By identifying problem paths, you can mitigate potential problems before investing time in place and route. You can redesign the logic paths to use less levels of logic, tag the paths for specialized routing resources, move to a faster device, or allocate more time for the path.

If logic-only-delays account for much less (<15%) than the total allowable delay for a path or timing constraint, then very low placement effort levels can be used by the place and route software. In these cases, reducing effort levels allow you to decrease runtimes while still meeting performance requirements.

Static Timing Analysis After Place and Route (FPGAs Only)

Post-PAR timing reports incorporate all delays to provide a comprehensive timing summary. If a placed and routed design has met all of your timing constraints, then you can proceed by creating configuration data and downloading a device. On the other hand, if you identify problems in the timing reports, you can try fixing the problems by increasing the placer effort level, using re-entrant routing, or using multi-pass place and route. You can also redesign the logic paths to use fewer levels of logic, tag the paths for specialized routing resources, move to a faster device, or allocate more time for the paths.

Edit the implementation template to modify the placer effort level. For information on re-entrant routing or multi-pass place and route, see the “Re-Entrant Routing” section at the end of this chapter.

Summary Timing Reports

Summary reports show timing constraint performance and clock performance. Implementing a design in the Flow Engine can automatically generate summary timing reports. To create summary timing reports, perform the following steps:

1. Open the Options dialog box (Implementation Implementation Options) from the Project Manager and select Edit Template for the Implementation template.
   
   
2. Select the Timing Reports tab.
   
   
3. For a post-map report, select Produce Logic Level Timing Report. For a post-PAR report select Produce Post Layout Timing Report.
   
   
4. To modify the reports to highlight path delays or paths that have failed timing constraints, select a report format.
   
   
5. After MAP or PAR has completed, the respective timing reports appear in the Report Browser.
   
   

Detailed Timing Analysis

To perform detailed timing analysis, select Tools Simulation/Verification Interactive Timing Analyzer from the Project Manager menu. You can specify specific paths for analysis, discover paths not affected by timing constraints, and analyze the timing performance of the implementation based on another speed grade. For path analysis, perform the following:

1. Choose sources. From the Timing Analyzer menu, select Path Filters Path Custom Filters Select Sources.
   
   
2. Choose destinations. From the Timing Analyzer menu, select Path Filters Path Custom Filters Select Destinations.
   
   
3. To create a report, select one of the options under the Analyze menu.
   
   

To switch speed grades, select Options Speed Grade. After a new speed grade is selected, all new Timing Analyzer reports will be based on the design running with new speed grade delays. The design does not have to be re-implemented, because the new delays are read from a separate data file.