This chapter guides you through a typical HDL-based design procedure using a design of a runner's stopwatch called Watch. The design example used in this tutorial demonstrates many device features, software features and design flow practices which you can apply to your own design. This design targets an XC4000E device; however, all of the principles and flows taught are applicable to any Xilinx device family, unless otherwise noted.
For an example of how to design with CPLDs, see the online help by selecting Help 
Foundation Help Contents from the Project Manager. Under Tutorials, select CPLD Design Flows.
In the first part of the tutorial, you use the Foundation design entry tools to complete the design. The design is composed of HDL elements and a LogiBLOX macro; you will synthesize the design using the Express tools.
Then, you will functionally simulate the design using the Foundation Logic Simulator. In the third part, you will implement the design using the Xilinx Implementation Tools. Finally, you will verify the design through timing simulation, and then download the bitstream to a Xilinx FPGA Demonstration Board. The simulation, implementation, and bitstream generation are described in subsequent chapters.
This chapter includes the following sections.
