The first design flow describes how to Floorplan your design after placing and routing your design. This is the preferred methodology because it allows you to view both the physical constraints for the design and the results of the automatic placement.
You enter your design using either a schematic capture tool or HDL. Next, run MAP and PAR to place and route the design in a target FPGA device. To view and improve performance of the automatic implementation, create a new Floorplan Netlist File within the Floorplanner from the placed and routed NCD file. Next, use the Floorplanner to constrain critical paths or adjust the automatic placement. Finally, run MAP and PAR with the newly generated MFP file to obtain the results of the floorplanned design. Refer to the design flow in the following figure.
Figure 2.1 PAR Before Floorplanning Design Flow |  |
