The second design flow is to floorplan your design before using PAR to place and route it. In this flow, you enter your design using either a schematic capture tool or HDL. Run MAP on the design to create a physical design file (NCD). Use the Floorplanner to define placement constraints by manually placing selected logic into the resources of the target device. Next, run MAP and PAR to fit the design into the target FPGA using the Floorplan constraints. Refer to the design flow in the following figure.
Figure 2.2 Floorplan First Design Flow |  |
