This chapter describes the four different design flows that you can use with the Floorplanner to implement your design in a Xilinx FPGA. Accompanying each design flow is a comprehensive flow chart that indicates the programs you use, the input files required, and output files that are generated. The four design flows are described in the following sections.
Xilinx strongly recommends that you read the HDL Synthesis and Simulation Design Guide before attempting to floorplan your HDL designs. This document explains HDL-specific design issues and understanding them will make floorplanning your HDL designs easier and more effective.
The design flows in this chapter present a general picture of where the Floorplanner fits in the Xilinx design flow; in some instances the descriptions of the design flows are more relevant to designers using schematic capture tools than to designers using HDL.
