Using the Xilinx Design Manager

The Xilinx Design Manager, a graphic design-flow and project manager, takes your design, represented by the EDIF file from EDIFNETO, and implements it in an FPGA or CPLD. You can also use the Xilinx Design Manager to generate timing information that you can import into ViewSim.

1. From the Windows toolbar, select Start Programs Xilinx Design Manager.
   
   The Xilinx Design Manager appears as shown in the figure that follows.
   
   

   Figure 8.49 Xilinx Design Manager

2. Select File New Project to create a new Xilinx project. In the New Project dialog box, use the Browse button to select calc.edn in your project directory. The Work Directory automatically fills in with the project directory, creating an xproject/calc.prj file in the your project directory.
   
   Each project has associated with it objects known as “versions” and “revisions.” Versions represent logic changes in a design (for example, adding a new block of logic, replacing an AND gate with an OR gate, or adding a flip-flop). Revisions represent different executions of the design flow on a single design version, usually with new implementation options (for example, higher place and route effort, a change in part type, or experimentation with new bitstream options). In the next stage, you make a new version and revision on which you run the implementation design flow.
   
   
3. In the Xilinx Design Manager, select Design Implement, which gives you the Implement dialog box, with fields for part type, design version, and revision. See the following figure.
   
   

   Figure 8.50 Implement Dialog Box

4. If you did not specify your part type on the top-level schematic, click the Select button to display a pull-down listing of available devices. Choose a Family of XC4000E, a Device of XC4003E, a Package of PC84, and a Speed Grade of -4. Click OK. The part number inserts into the Part field in the Implement dialog box.
   
   
5. Click on Options. The Options dialog box appears. See the next illustration.
   
   

   Figure 8.51 Options Dialog Box

6. Click Browse next to the User Constraints field. Select the calc_4ke.ucf file from the design directory, then Click OK.
   
   
7. Under Optional Targets, ensure selection of the following options.
   
   
   • Produce Timing Simulation Data - generates a back-annotated EDIF netlist imported into the Viewlogic tools.
     
     
   • Produce Configuration Data - generates a programming bitstream suitable for downloading into the Xilinx device.
     
     
   • Produce Post Layout Timing Report - generates a timing report file based on how the design actually routes.
     
     You can also select the following option.
     
     
   • Produce Logic Level Timing Report - generates a preliminary (pre-place and route) timing report based on the number of logic levels in each signal path. It generates before the place-and-route layout step, so it does not contain information on device routing. Look at this report before place and route to see how much “routing slack” exists in a design.
     
     
8. Under Program Option Templates Implementation, select Edit Template. The XC4000 Implementation Options dialog box appears.
   
   
9. Select the Interface tab. In the Interface pane, look under Simulation Data Options and verify that Format is set to EDIF and that Correlate Simulation Data to Input Design is selected. In the Vendor field, select Viewlogic.
   
   
10. Click OK to return to the Options window. Click OK to return to the Implementation dialog box.
    
    
11. Verify that the version is “ver1” and the revision is “rev1” then click Run. The Flow Engine comes up as shown in the next figure.
    
    

    Figure 8.52 The Xilinx Flow Engine

    The status bar shows the progress of the implementation flow with the following stages.
    
    
    • Translate - convert the design EDIF file into an NGD (Native Generic Design) file
      
      
    • Map - group basic elements (“bels”) such as flip-flops and gates into logic blocks (“comps”); also generate a logic-level timing report if desired
      
      
    • Place & Route - place components into the device, and route signals between them
      
      
    • Timing - generate timing simulation data and an optional post-layout timing report
      
      
    • Configure - generate a bitstream suitable for downloading into and configuring a device
      
      
12. When the implementation completes, an Implementation Status box appears with the following message.
    
    Implementing revision ver1->rev1 completed successfully.
    
    
13. Click on View Logfile to display the logfile from Flow Engine. The report displays in Wordpad. Click OK in the Implementation Status dialog to return to the Xilinx Design Manager.
    
    

NOTE

To use another text editor as the report viewer, select File Preferences from the Xilinx Design Manager.

This completes the tutorial design process.