Language Constructs

One of the components of the VHDL synthesis process is the set of VHDL constructs that describes your design and determines its architecture, and, at the same time, giving consistently good results. The remainder of this guide discusses these constructs and their uses.

The concepts mentioned earlier in this chapter are described in the guide as follows.

• Design Hierarchy
  
  The chapter “Describing Designs” describes the use and importance of hierarchy in VHDL designs. The chapter “Concurrent Statements” explains how to instantiate (apply) existing components.
  
  
• Data Types
  
  The chapter “Data Types” describes data types and their uses.
  
  
• Register Selection
  
  

You can instantiate registers with the component instantiation statement discussed in the “Describing Designs” chapter and the “Concurrent Statements.” chapter. The “Sequential Statements” chapter and the “Register and Three-State Inference” chapter describe register inference with the VHDL if and wait statements.