Sync I/O Constraints (2)
Consider constraints on the I/O
Example:
Data is clocked by signal CLK on all ICs
Frank is creating IC2
All inputs and outputs of IC2 are synchronized to CLK
How are inputs and outputs constrained?
IC2: Device under
Development
IC 1
IC 3
D
CK
Q
C2
C3
C1
C4
D
CK
Q
CLK
D
CK
Q
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