1. If necessary, double-click the targeted device and select Virtual Device (the default for new projects).
2. Highlight EDIF Netlist for External Fitter and select Process -> Properties.
3. Click on the Value column for I/O Buffer Insertion and set to Macro-level. Click OK.
4. Select Process -> Run to create a macro-level EDIF netlist for the ABEL design, including all ABEL hierarchy modules.
You can now create a symbol for the ABEL macro and use it in a schematic design using a schematic entry tool that you provide. The macro symbol should be named the same as your ABEL project file name (without the .npl extension). The symbols should contain pins that match the names of the pins declared in your (top-level) ABEL module.
After you complete your schematic design and convert it to a netlist, invoke the Xilinx Design Manager (CPLD Fitter Tools icon from the WebPACK program group) to implement your design in a CPLD device.
Continue
with Simulating a New Design