Fitting the jc2_abl Design

1. To fit the design, select a device from the screen by double-clicking the targeted device icon  in the Sources window. (The XC9536XL CS48 is already selected for this tutorial.) The following display will appear.

2. To select the CPLD device family, select the Value box to the right of the Vendor Name property. You should select Xilinx 9500XL CPLDs in the drop-down list. To select the target device, select the Value box on the second property line, which should now be named after the selected family. You should select XC9536XL CS48 in the drop-down list.

3. Click OK. The Project Navigator will display as follows:

4. Highlight the Fit Design process and select Process - Run to run the Xilinx CPLD fitter. The fitter will run and the transcript will display the progress and success of the fit.

5. After the fitter has finished running, you may examine reports. The results of the fitter are found in the Fitter Report and the Timing Report. To examine a report simply double-click the name of the report.

6. For instance, double-click on Fitter Report.

The fitter report will display in the Report Viewer.

Note: The Lock Pins step should only be run when you want to commit your design to a previously established pinout before running design iterations.

Continue with Simulating the Design