Speeding Up fMAX with Local Feedback

Use timing constraints to specify fMAX. The timing constraint to specify fMAX from flip-flop RegX to flip-flop RegY would look like the following (assuming RegX and RegY are the names of the output nets produced by the 2 registers):

TS01=FROM:FFS(RegX):TO:FFS(RegY):12

See Using Timing Constraint Driven Optimization for a complete description of how to use timing constraints for CPLD designs.

The fitter will attempt to group the two registers into the same function block to use the local feedback path between them. If you need to explicitly group flip-flops RegX and RegY into the same function block, you could use the LOC attribute. If there is also combinatorial logic between these flip-flops that was not optimized (resulting in multi-level logic between the flip-flops) you should also group the combinatorial logic into the same function block. To place these functions in function block 1, including the un-optimized logic represented by GATE, the required LOC properties would look like this:

Using ABEL:

The block property can be used to apply an arbitrary attribute string, such as the LOC attribute, to an individual design element in the netlist from ABEL.

xilinx property ‘BLOCK RegX LOC=FB1’;

xilinx property ‘BLOCK RegY LOC=FB1’;

xilinx property ‘BLOCK GATE LOC=FB1’;

Using UCF File (for VHDL or Verilog designs):

INST RegX LOC=FB1;

INST RegY LOC=FB1;

NET GATE LOC=FB1;