Using Timing Constraint Driven Optimization

The CPLD fitter can optimize designs based on your timing constraints. Timing constraints are useful for controlling optimization when you have complex multi-level logic in your design. These constraints give the CPLD fitter more information about your design’s timing requirements and enable it to reduce logic levels and allocate resources to meet those requirements. You do not always need to specify time constraints to achieve your design goals, but when you do need more control of optimization, timing constraints allow you to specify:

The maximum external pad to pad delay (tPD )

The minimum required operating frequency (fMAX )

The minimum required setup time for flip-flops (tSU )

The maximum external clock pad to output pad delay (tCO )

Timing constraint specifications (timespecs) can be entered directly in a User Constraints File (.UCF) for any type of design, including ABEL.

For a complete description of timing constraint syntax, refer to the Attributes chapter of the Libraries Guide in the Xilinx online book collection. For basic instructions on how to enter timespecs, see Entering T-Specs in a UCF file

Grouping Signals

Using XC9500 Local Function Block Feedback