Speeding Up tCO with Local Feedback

Use timing constraints to specify tCO. The timing constraint to specify tCO from the input controlling flip-flop RegX to output pad Out would look like:

TS01=FROM:PADS(Clock):TO:PADS(Out):15

See Using Timing Constraint Driven Optimization for a complete description of how to use timing constraints for CPLD designs.

The fitter will attempt to group the register and the gate function into the same function block to use the local feedback path between them. If you need to explicitly group register RegX and output Out into the same function block, you can use the LOC attribute. To place both of these functions in function block 1, the Xilinx property LOC statement would look like this:

Using ABEL:

The BLOCK property can be used to apply an arbitrary attribute string, such as the LOC attribute, to an individual design element in the netlist from ABEL.

xilinx property ’BLOCK RegX LOC=FB1’;

xilinx property ‘BLOCK Out LOC=FB1’;

Using UCF File (for VHDL or Verilog designs):

INST RegX LOC=FB1;

NET Out LOC=FB1;