The XChecker hardware consists of a cable assembly with internal logic, a test fixture, and a set of headers to connect the cable to your target system. The cable can be used with a single FPGA or CPLD, or several devices connected in a daisy chain.
Using the XChecker hardware requires either a standard DB-9 or DB-25 RS-232 serial port. If you have a different serial port connection, you need to provide a DB-9/DB-25 adapter.
The XChecker Cable is shipped with two sets of flying lead wires. The flying lead connectors have a nine position header connector on one end. The other end has eight individual wires with female connectors that fit onto standard 0.025 inch square male pins.
The following figure shows the XChecker cable hardware and flying lead connection wires.
Figure 3.1 XChecker Cable and Flying Leads |  |
The following figure shows top and bottom views of the XChecker cable.
Figure 3.2 XChecker Cable | |
The plastic cover of the XChecker cable is beige, while the cover for the Parallel Cable III is grey.
The flying lead wires are keyed to fit into the appropriate cable header. Use Header 1 for FPGAs and Header 2 for CPLDs.
Communication between your host system and the XChecker Cable is dependent on host system capability. The XChecker Cable supports several Baud rates and platforms, as shown in the following table.
| Platform | 9600 | 19200 | 38400 | 115.2K |
|---|---|---|---|---|
| IBM® PC | X | X | X | X |
| NEC PC | X | |||
| SUN® | X | X | X | |
| HP 700 | X | X | X | X |
| X indicates applicable baud rate | ||||
TRST is an optional pin in the JTAG (IEEE 1149.1) specification, and is not used by XC9500 CPLDs. If any of your parts have a TRST pin, the pin should be connected to VCC.
The following table describes the CPLD pin connections to the target circuit board.
| Name | Function | Connections |
|---|---|---|
| VCC | Power - Supplies VCC (5 V, 100 mA, typically) to the cable | To target system VCC |
| GND | Ground - Supplies ground reference to the cable | To target system ground |
| RD (TDO) | Read Data - Reads back data from the target system is read at this pin. | Connect to system TDO pin. |
| TDI | Test Data In - this signal is used to transmit serial test instructions and data. | Connect to system TDI pin. |
| TCK | Test Clock - this clock drives the test logic for all devices on boundary-scan chain. | Connect to system TCK pin. |
| TMS | Test Mode Select - this signal is decoded by the TAP controller to control test operations. | Connect to system TMS pin. |
| CLKI | Not used. | Unconnected. |
| CLKO | Not used. | Unconnected. |
| CCLK | Not used. | Unconnected. |
| D/P | Not used. | Unconnected. |
| DIN | Not used. | Unconnected. |
| PROG | Not used. | Unconnected. |
| INIT | Not used. | Unconnected. |
| RST | Not used. | Unconnected. |
| RT | Not used. | Unconnected. |
| TRIG | Not used. | Unconnected. |
This section details the connections needed to configure FPGAs with the XChecker Cable.
If you are using the Xilinx FPGA Design Demonstration Board, see the “Mode Switch Settings” section of the “FPGA Design Demonstration Board” chapter for specific configuration information.
HR SIZE="2" WIDTH="100%" ALIGN="center" NOSHADE>The following figures show which pins to connect, depending on your chosen FPGA device. For descriptions of each pin, see the “XChecker/Parallel Cable III Connector (J2)” table and the “XChecker/Parallel Cable III Connector J1” table.
Use Header 1 (see the “XChecker Cable and Flying Leads” figure) to connect the XChecker cable to the target system for configuring FPGAs. When configuring XC4000 FPGAs, the RST (Reset) wire is not used as shown in the following figure.
Figure 3.3 XChecker Connections to XC4000 Device | |
To configure XC3000 FPGAs, the PROG wire is not used. This is shown in the following figure. In both cases, the FPGA must be in the Serial Slave Mode.
Figure 3.4 XChecker Connections to XC3000 Device | |
