Appendix D

Simulation Summary

This appendix contains the following sections on simulation:

• “Timing Simulation” section
  
  
• “Simulation from Design Manager” section
  
  
• “Simulation on Workstation Command LIne” section
  
  
• “Simulating Power-On Initialization” section
  
  

Timing Simulation

The Design Manager/Flow Engine can produce timing simulation data for use in a third party simulation tool.

This section describes how to prepare a simulation model file for functional and timing simulation in the Design Manager and Workstation command line environments.

Simulation from Design Manager

The Design Manager will produce timing simulation data automatically when you run the fitter. To produce timing simulation go to the Setup Options template and check the box labelled Produce Timing Simulation Data. A timing simulation netlist will be automatically generated when the Flow Engine runs.

Figure D.1 Options

By default the simulation data will be produced in EDIF format. Format is set from the Implementation Options dialog box; if you want to select another format, go to the Interface tab and click on the down arrow adjacent to Format, then select from the supported formats.

When you implement the design, the Flow Engine produces timing simulation data files. Each time the data is produced, it is automatically exported to your design directory.

You can now use these files to simulate the design with a supported third party simulation tool.

Simulation on Workstation Command LIne

The commands ngd2vhdl and ngd2ver and ngd2edif give you the ability to simulate vhdl, verilog, and edif designs on a workstation command line. See the Development System Reference Guide for instructions on using these three programs.

NGD2EDIF

The NGD2EDIF program produces an EDIF 2.0.0 netlist in terms of the Xilinx primitive set, allowing you to simulate pre- and post-route designs.

Syntax

To invoke the NGD2EDIF translation program from the UNIX or DOS command line, enter the following:

ngd2edif [options] infile[.ngd|.nga] [outfile[.edn]]

where:

Options can be any number of the NGD2EDIF options listed in this section. They do not need to be listed in any particular order. Separate multiple options with spaces.

infile[.ngd|.nga] indicates the input file. If you enter a file name with no extension, NGD2EDIF looks for a file with an .nga extension and the name you specified. If you want to translate an NGD file, you must enter the .ngd extension. Without the .ngd extension NGD2EDIF does not use the NGD file as input, even if there is no NGA file present.

outfile[.edn] is the name of NGD2EDIF's output file if you want to name it other than the root NGD design name. If you do not give an extension, .edn is added.

If you are using the Viewlogic design entry tools, it is important that the outfile name be different from the original design name, to avoid conflict with the original WIR and EDIF files.

Options

• -a (Write All Properties)
  
  The -a option causes NGD2EDIF to write all properties into the output EDIF netlist. The default is to write only timing delay properties and certain other properties that define the behavior of the design logic. In most cases the -a option is not necessary; your simulation vendor can tell you if it is required for the vendor's flow.
  
  
• -n (Generate Flattened Netlist)
  
  The -n option writes out a flattened netlist.
  
  
• -v (Vendor)
  
  -v vendor
  
  The -v option specifies the CAE vendor toolset that uses the resulting EDIF file. Allowable entries are viewlog (for Viewlogic) and mentor.
  
  The -v option customizes the output EDIF file for the specified vendor's simulator.
  
  
• -w (Overwrite Output)
  
  

The -w option indicates to overwrite the output file.

NGD2VHDL

The NGD2VHDL program translates your design into a VITAL 95 IEEE compliant VHDL file containing a netlist description of the design in terms of Xilinx simulation primitives. The VHDL file can be used to perform a back-end simulation by a VHDL simulator.

Syntax

The following syntax translates your design to a VHDL file:

ngd2vhdl [options] infile.[ngd|.nga] [outfile[.vhd]]

where:

Options can be any number of the NGD2VHDL options listed in this section. They do not need to be listed in any particular order. Separate multiple options with spaces.

Infile [.ngd|.nga] is the input NGD or NGA file. If you enter a file name with no extension, NGD2VHDL looks for a file with an .nga extension and the name you specified. If you want to translate an NGD file, you must enter the .ngd extension. Without the .ngd extension NGD2VHDL does not use the NGD file as input, even if there is no NGA file present.

Outfile[.vhd] indicates the file to which the VHDL output of NGD2VHDL is written. Default is infile.vhd (infile is the same root name as the input file). The SDF file has the same root name as the VHDL file.

Options

• -gp (Bring Out Global Reset Net as Port)
  
  The -gp option causes NGD2VHDL to bring out the global power-on simulation signal (which is connected to all flip-flops and latches in the physical design) as a port on the top-level entity in the output VHDL file name PRLD.
  
  If you do not specify the -gp option, the output.vhd file will contain an ROC cell which automatically pulses the internal PRLD net at the beginning of the simulation sequence.
  
  
• -tb (Generate Testbench File)
  
  The -tb option writes out a testbench file. The file has a .tvhd extension.
  
  The default top-level instance name within the testbench file is UUT. If you enter a -ti (Top Instance Name) option, the top-level instance name is the name specified by the -ti option.
  
  
• -w (Overwrite Existing Files)
  
  

The -w option causes NGD2VHDL to overwrite the output files if they already exist. By default (no -w specified) NGD2VHDL does not overwrite existing files.

NGD2VER

The NGD2VER program translates your design into a Verilog HDL file containing a netlist description of the design in terms of Xilinx simulation primitives. The Verilog file can be used to perform a back-end simulation by a Verilog simulator.

Syntax

The following syntax translates your design to a Verilog file:

ngd2ver [options] infile[.ngd|.nga] [outfile[.v]]

Options can be any number of the NGD2VER options listed in this section. They do not need to be listed in any particular order. Separate multiple options with spaces.

Infile [.ngd|.nga] is the input NGD or NGA file. If you enter a file name with no extension, NGD2VER looks for a file with an .nga extension and the name you specified. If you want to translate an NGD file, you must enter the .ngd extension. Without the .ngd extension NGD2VER does not use the NGD file as input, even if there is no NGA file present.

Outfile[.v] indicates the file to which the Verilog output of NGD2VER is written. Default is infile.v (infile is the same root name as the input file). The SDF file has the same root name as the Verilog file.

Options

• -gp (Bring Out Global Reset Net as Port)
  
  The -gp option causes NGD2VER to bring out the global power-on simulation signal (which is connected to all flip-flops and latches in the physical design) as a port on the top-level module in the output Verilog file named PRLD.
  
  
• -tf (Generate Test Fixture File)
  
  The -tf option generates a test fixture file. The file has a .tv extension, and it is a ready-to-use template test fixture Verilog file based on the input NGD or NGA file.
  
  If you are using a Cadence Verilog simulator, you can run the simulator by entering
  
  verilog design.tv design.v,
  
  using the output V and TV files from NGD2VER. You can then add more design-specific stimuli to this file to fit your needs.
  
  
• -w (Overwrite Existing Files)
  
  

The -w option causes NGD2VER to overwrite the output files if they already exist. By default (no -w specified) NGD2VER does not overwrite existing files.

Simulating Power-On Initialization

The XC9000 component library for all tools directly supported by Xilinx and most third-party tools contain functional simulation models for all of the primitive symbols. Models for registered components contain a global net named PRLD that will reset the registers to zero when pulsed high at the beginning of functional simulation.

In the timing simulation netlists produced by the software, a net named PRLD is added to the design to represent the device power-on condition. When this PRLD net is pulsed high, all registers in the device are initialized to the states specified by INIT attributes in your design.

To simulate the XC9000 device power-on condition, set the PRLD net input to the High state at time zero. Set PRLD Low after any positive time interval.

Registers are initialized instantaneously (zero delay from PRLD to registers) and are held at the initial state as long as PRLD is High. Registers are allowed to change state in response to user stimulus any time after PRLD is set Low. Before setting PRLD Low, you should set all essential device inputs to valid logic values to prevent registers from lapsing back into the “unknown” state. You should hold your device inputs at valid logic values long enough to propagate to all the registers before returning PRLD low.

In EDIF simulation netlists, PRLD is a global internal signal. If you are simulating based on an EDIF output file (.edn), you must drive the PRLD signal low throughout the remainder of your simulation. Otherwise the registers in the design will remain stuck in the unknown state.

If you create a VHDL or Verilog HDL timing simulation netlist, it will also contain a PRLD net used to initialize all the registers in the design. The PRLD net will be driven by either a pullup resistor, for Verilog HDL netlists, or by a Reset-on-Configuration (ROC) pulse generator for VHDL netlists, unless you bring it out as a port by specifying the -gp option on the ngd2vhdl or ngd2ver command line.