XC3000 Configuration Options

Click the Configuration, Startup/Readback, or Tie tab to access the different options within the Configuration Options dialog box. These options affect the Configure step in the implementation flow. Use the different tabs of this dialog box to set the options described in the following sections.

• “XC3000 Configuration Tab”
  
  
• “XC3000 Startup/Readback Tab”
  
  
• “XC3000 Tie Tab”
  
  

Click OK to accept the options, click Cancel to exit the dialog box without changing any settings, click Default to set the default options, or click Help to obtain online help.

XC3000 Configuration Tab

Use this tab, shown in the following figure, to set the following options.

Figure 5.39 XC3000 Configuration Tab

Threshold Level - Inputs

Specify one of the following input options. The default is Read from Design.

• TTL
  
  Select TTL to specify TTL-compatible inputs except for the special purpose clocks, Tclkin, Bclkin, and Pwrdwn which require CMOS input signals.
  
  
• CMOS
  
  Select CMOS to specify CMOS compatible inputs.
  
  
• Read from Design
  
  Select Read from Design to specify the TTL/CMOS input level included in the physical contraints (PCF) file.
  
  

Configuration Pin Pullups - Done/Program

Specify one of the following options. The default is Pullup.

• Float
  
  This option disables an internal pull-up resistor on the Done/Program (D/!P) pin. The D/!P pin is an open-drain output that requires a pull-up resistor to indicate the end of the configuration. If this option is selected, an external pull-up resistor should be connected to the D/!P pin.
  
  
• Pullup
  
  This option enables an internal pull-up resistor on the Done/Program (D/!P) pin. This resistor has a value of 2 to 8 kilohms. The D/!P pin configures an open-drain driver that requires a pull-up resistor to indicate the end of the configuration. Turn off this option only if you intend to connect an external pull-up resistor to this pin.
  
  

Crystal Oscillator

The XC3000 family of devices contains an internal high-speed inverting amplifier which you can use to implement an on-chip crystal oscillator. To use this feature, you must include either the GXTL or OSC library element in your design and connect the appropriate external R-C crystal circuit to the amplifier. See the Xilinx Libraries Guide and The Programmable Logic Data Book for more information.

Select one of the following options. The default is Disabled.

• Disabled
  
  Select Disabled to disable the crystal oscillator.
  
  
• Enabled
  
  Select Enabled to enable the crystal oscillator.
  
  
• Enabled (Divide by 2)
  
  Select Enabled (Divide by 2) to divide the crystal oscillator frequency by two to generate a symmetrical clock signal.
  
  

Produce ASCII Configuration File

This option creates a rawbits (RBT) file in addition to the binary BIT file. The RBT file is a text file that contains ASCII 1s and 0s. These characters represent the actual bits in the configuration bitstream that are downloaded to the FPGA. By default, this option is off.

XC3000 Startup/Readback Tab

Use this tab, shown in the following figure, to set the following options.

Figure 5.40 XC3000 Startup/Readback Tab

Readback - Mode

After an FPGA is configured, data can be read back and compared with the original configuration data. For security reasons it is sometimes desirable to disable or limit readback capability. The following options control readback. The default is On Command.

• Never
  
  Select Never to disable readback.
  
  
• Once
  
  Select Once to enable a one-time readback.
  
  
• On Command
  
  Select On Command to enable readback on command. This option generates a .ll file.
  
  

Output Events

The Output Events group box contains the following options.

• Done
  
  The DONE signal indicates the completion of the configuration sequence. You can program this signal to be asserted before or after I/Os go active. The default is Before I/Os Active.
  
  
  • Before I/Os Active
    
    Select Before I/Os Active to release the DONE signal one Cclk period before the outputs go active.
    
    
  • After I/Os Active
    
    Select After I/Os Active to release the DONE signal one Cclk period after the outputs go active.
    
    
• Reset
  
  A global reset signal is asserted while the device is configuring during the startup sequence. You can program the release of this signal to occur before or after I/Os go active. The default is After I/Os Active.
  
  
  • Before I/Os Active
    
    Select Before I/Os Active to release the Internal Reset one Cclk period before the outputs go active.
    
    
  • After I/Os Active
    
    Select After I/Os Active to release the Internal Reset one Cclk period after the outputs go active.
    
    

XC3000 Tie Tab

Use this tab, shown in the following figure, to set the tie options.

Figure 5.41 XC3000 Tie Tab

The XC3000 Tie tab is identical to the tab described in the “Spartan Tie Tab” section.