XC3000 Simulation Options

Click the General, VHDL/Verilog, or EDIF tab to access the different options within the Simulation Options dialog box. These options affect the timing simulation data produced during the Timing (Sim) step of the implementation flow. Use the different tabs of this dialog box to set the options described in the following sections.

Click OK to accept the options, click Cancel to exit the dialog box without changing any settings, click Default to set the default options, or click Help to obtain online help.

XC3000 General Tab

Use this tab, shown in the following figure, to set the general simulation options.

Figure 5.36 XC3000 General Tab

The XC3000 General tab is identical to the tab described in the “Spartan General Tab” section.

XC3000 VHDL/Verilog Tab

Use this tab, shown in the following figure, to set the VHDL or Verilog options.

Figure 5.37 XC3000 VHDL/Verilog Tab

Bring Out Global Set/Reset Net as a Port

This option creates a Global Set/Reset port on the top-level simulation module (entity). This port is connected to all flip-flop and latch primitives in the design. Stimulating this port automatically sets or resets every flip-flop and latch to its initial state, as determined in the design. The default name of the Global Set/Reset port depends on the target device family as described in the “Global Set/Reset Port Information” table.

Use the Port Name field to change the default port name. Specifying the port name allows you to match the port name you used in the front end.

Generate Test Fixture/Testbench File

This option writes out a Verilog test fixture file or a VHDL testbench file. The test fixture file has a .tv extension. The testbench file has a .tvhd extension.

Include `uselib Directive in the Verilog File

This option writes a library path pointing to the SimPrim library into the output Verilog (.v) file. The path is written as follows, where $XILINX is the location of the Xilinx software.

`uselib dir=$XILINX/verilog/data libext=.vmd

Note: This option is supported for Verilog only.

Generate Pin File

This option writes out a signal-to-pin mapping file. The file has a .pin extension.

Retain Hierarchy in Netlist

This option writes out a Verilog HDL or VHDL file that retains the hierarchy in the original design. The option groups logic based on the original design hierarchy.

Rename Architecture Name to

This option allows you to rename the architecture name generated in your VHDL file. The default architecture name for each entity in the netlist is STRUCTURE.

XC3000 EDIF Tab

Use this tab, shown in the following figure, to set the EDIF options.

Figure 5.38 XC3000 EDIF Tab

The XC3000 EDIF tab is identical to the tab described in the “Spartan EDIF Tab” section.