Virtex Configuration Options

Click the Configuration, Startup, or Readback tab to access the different options within the Configuration Options dialog box. These options affect the Configure step in the implementation flow. Use the different tabs of this dialog box to set the options described in the following sections.

• “Virtex Configuration Tab”
  
  
• “Virtex Startup Tab”
  
  
• “Virtex Readback Tab”
  
  

Click OK to accept the options, click Cancel to exit the dialog box without changing any settings, click Default to set the default options, or click Help to obtain online help.

Virtex Configuration Tab

Use this tab, shown in the following figure, to set the following options.

Figure 5.29 Virtex Configuration Tab

Configuration Rate

Virtex uses an internal configuration clock, CCLK, when configuring in a master mode. Use the configuration rate option to select the rate in megahertz (MHz) for this clock. The default is 4MHz.

Configuration Pins

The Configuration Pins group box contains the following options.

• Configuration Clk
  
  This pin is used to synchronize to an internal clock provided in the FPGA device. The default is PullUp.
  
  
  • Float
    
    Select Float to disable the pull-up resistor on the Configuration Clk pin.
    
    
  • PullUp
    
    Select PullUp to enable a pull-up on the Configuration Clk pin.
    
    
• M0
  
  The M0 pin is used to determine the configuration mode. The value of the pull-up and pull-down resistors is 50 to 100 kilohms. The following options are available. The default is PullUp.
  
  
  • Float
    
    Select Float to disable both the pull-up resistor and pull-down resistor on the M0 pin.
    
    
  • PullUp
    
    Select PullUp to enable a pull-up on the M0 pin.
    
    
  • PullDown
    
    Select PullDown to enable a pull-down on the M0 pin.
    
    
• M1
  
  The M1 pin can be used as tristatable output pin. The value of the pull-up and pull-down resistors is 50 to 100 kilohms. The following options are available. The default is PullUp.
  
  
  • Float
    
    Select Float to disable both the pull-up resistor and pull-down resistor on the M1 pin.
    
    
  • PullUp
    
    Select PullUp to enable a pull-up on the M1 pin.
    
    
  • PullDown
    
    Select PullDown to enable a pull-down on the M1 pin.
    
    
• M2
  
  The M2 pin is used to determine the configuration mode. The value of the pull-up and pull-down resistors is 50 to 100 kilohms. The following options are available. The default is PullUp.
  
  
  • Float
    
    Select Float to disable both the pull-up resistor and pull-down resistor on the M2 pin.
    
    
  • PullUp
    
    Select PullUp to enable a pull-up on the M2 pin.
    
    
  • PullDown
    
    Select PullDown to enable a pull-down on the M2 pin.
    
    
• Program
  
  The !PROG pin allows device reprogramming. The value of the pull-up resistor is 50 to 100 kilohms. The default is PullUp.
  
  
  • Float
    
    Select Float to disable both the pull-up resistor and pull-down resistor on the !PROG pin.
    
    
  • PullUp
    
    Select Pullup to enable a pull-up on the !PROG pin.
    
    
• Done
  
  The DONE pin configures an open-drain driver that requires a pull-up resistor to indicate the end of the configuration. The value of the pull-up resistor is 2 to 8 kilohms. The following options are available. The default is PullUp.
  
  
  • Float
    
    Select Float to disable the pull-up resistor on the DONE pin. If you select this option, be sure you have connected an external pull-up resistor to this pin.
    
    
  • PullUp
    
    Select PullUp to enable an internal pull-up resistor on the DONE pin. Select this option only if you do not connect an external pull-up resistor to this pin.
    
    
  • Active PullUp
    
    Select Active PullUp to drive the DONE pin High with a CMOS driver.
    
    

JTAG Pins

The JTAG group box contains the following options. For more information on the following pins, see the JTAG Programmer Guide.

• TCK
  
  This pin is the JTAG test clock.The default is PullUp.
  
  
  • Float
    
    Select Float to disable both the pull-up resistor and pull-down resistor on the TCK pin.
    
    
  • PullUp
    
    Select PullUp to enable a pull-up on the TCK pin.
    
    
  • PullDown
    
    Select PullDown to enable a pull-down on the TCK pin.
    
    
• TDI
  
  This pin is the serial data input to all JTAG instructions and JTAG registers. The default is PullUp.
  
  
  • Float
    
    Select Float to disable both the pull-up resistor and pull-down resistor on the TDI pin.
    
    
  • PullUp
    
    Select PullUp to enable a pull-up on the TDI pin.
    
    
  • PullDown
    
    Select PullDown to enable a pull-down on the TDI pin.
    
    
• TDO
  
  The TDO pin is the serial data output for all JTAG instruction and data registers. The default is Float.
  
  
  • Float
    
    Select Float to disable both the pull-up resistor and pull-down resistor on the TDO pin.
    
    
  • PullUp
    
    Select PullUp to enable a pull-up on the TDO pin.
    
    
  • PullDown
    
    Select PullDown to enable a pull-down on the TDO pin.
    
    
• TMS
  
  This pin is the mode input signal to the TAP controller. The TAP controller provides the control logic for JTAG. The default is PullUp.
  
  
  • Float
    
    Select Float to disable both the pull-up resistor and pull-down resistor on the TMS pin.
    
    
  • PullUp
    
    Select PullUp to enable a pull-up on the TMS pin.
    
    
  • PullDown
    
    Select PullDown to enable a pull-down on the TMS pin.
    
    

Produce ASCII Configuration File

This option creates a rawbits (RBT) file in addition to the binary BIT file. The RBT file is a text file that contains ASCII 1s and 0s. These characters represent the actual bits in the configuration bitstream that are downloaded to the FPGA. By default, this option is off.

Enable the User ID Code

Use this option to assign a code in the User Identification Register. Enter an ID code in the Code field. This code comprises eight hexadecimal digits that are placed in the User ID Register. By default, this option is off.

Virtex Startup Tab

Use this tab, shown in the following figure, to set the following options.

Figure 5.30 Virtex Startup Tab

Start-up Clock

The startup sequence following the configuration of a device can be synchronized to either CCLK, a User Clock, or the JTAG Clock. The default is CCLK.

• CCLK
  
  Select CCLK to synchronize to an internal clock provided in the FPGA device.
  
  
• User Clock
  
  Select User Clock to synchronize to a user-defined signal connected to the CLK pin of the startup symbol. You must select this option if your design contains a user clock net that drives the CLK pin on startup.
  
  
• JTAG Clock
  
  Select JTAG Clock to synchronize to the clock provided by JTAG. This clock sequences the TAP controller which provides the control logic for JTAG.
  
  

Output Events

There are five major output events which occur during a device startup.

• Done (CFG_DONE pin going High)
  
  
• Enable Outputs (device outputs no longer tristated)
  
  
• Release Set/Reset (Global Set/Reset signal deasserted)
  
  
• Release Write Enable (Global Write Enable signal deasserted)
  
  
• Release DLL (DLL allowed to synchronize)
  
  

Depending on the settings for Startup Clock, the output events can be set to occur as shown in the following table. For more information, see The Programmable Logic Data Book.

Table 5_3 Output Events Options Matrix

The definitions of the possible output events settings are as follows.

C0 - before the Cclk rising edge after the length count is met

C1 - first-Cclk rising edge after the length count is met

C2 - second-Cclk rising edge after the length count is met

C3 - third-Cclk rising edge after the length count is met

C4 - fourth-Cclk rising edge after the length count is met

C5 - fifth-Cclk rising edge after the length count is met

C6 - sixth-Cclk rising edge after the length count is met

U2 - second-valid-user-clock rising edge after C1 (first-Cclk rising edge after length count is met)

U3 - third-valid-user-clock rising edge after C1 (first-Cclk rising edge after length count is met)

U4 - fourth-valid-user-clock rising edge after C1 (first-Cclk rising edge after length count is met)

U5 - fifth-valid-user-clock rising edge after C1 (first-Cclk rising edge after length count is met)

U6 - sixth-valid-user-clock rising edge after C1 (first-Cclk rising edge after length count is met)

J2 - second-valid-JTAG-clock rising edge after C1 (first-Cclk rising edge after length count is met)

J3 - third-valid-JTAG-clock rising edge after C1 (first-Cclk rising edge after length count is met)

J4 - fourth-valid-JTAG-clock rising edge after C1 (first-Cclk rising edge after length count is met)

J5 - fifth-valid-JTAG-clock rising edge after C1 (first-Cclk rising edge after length count is met)

J6 - sixth-valid-JTAG-clock rising edge after C1 (first-Cclk rising edge after length count is met)

Done - when the CFG_DONE signal goes High

Keep - holds the pin at whatever level (High or Low) the pin is when the CFG_DONE signal goes High

No Wait - not synchronized to the startup clock; DLL synchronizes as soon as possible

Enable Internal Done Pipe

Select this option when the startup clock is running at high speeds. If you select this option, the FPGA waits for the CFG_DONE signal that is delayed by one clock cycle instead of waiting for the pin itself. By default, this option is off.

Virtex Readback Tab

Use the Readback tab, shown in the following figure, to set the configuration readback options.

Figure 5.31 Virtex Readback Tab

Security

• Enable Readback and Reconfiguration
  
  This option specifies readback options. After the FPGA design has been configured, the FPGA configuration data can be read back and compared with the original configuration data. Readback is initiated by a Low-to-High transition on the M0/RTRIG pin. After this option is run, external logic must drive the Cclk input to read back each data bit. The readback data appears on the !RDATA pin.
  
  Select Generate Readback Bitstream to create a byte wide readback bitstream file. By default, this option is off.
  
  
• Disable Readback
  
  This option disables readback. Use this option for design security. By disabling readback, configuration data is secure from being read from the FPGA. By default, this option is off.
  
  
• Disable Readback and Reconfiguration
  
  This option disables both readback and reconfiguration. Use this option for design security. By disabling readback and reconfiguration, configuration and reconfiguration data is secure from being read from the FPGA. By default, this option is off.