XC3000 Implementation Options

Click the Translate, Optimize and Map, Place and Route, or Timing Reports tab to access the different options within the Implementation Options dialog box. These options affect the Translate, Map, and Place&Route steps in the implementation flow. Use the different tabs of this dialog box to set the options described in the following sections.

• “XC3000 Translate Tab”
  
  
• “XC3000 Optimize and Map Tab”
  
  
• “XC3000 Place and Route Tab”
  
  
• “XC3000 Timing Reports Tab”
  
  

Click OK to accept the options, click Cancel to exit the dialog box without changing any settings, click Default to set the default options, or click Help to obtain online help.

XC3000 Translate Tab

Use this tab, shown in the following figure, to set the translate options.

Figure 5.32 XC3000 Translate Tab

The XC3000 Translate tab is identical to the tab described in the “Spartan Translate Tab” section.

XC3000 Optimize and Map Tab

Use this tab, shown in the following figure, to set the following options.

Figure 5.33 XC3000 Optimize and Map Tab

Logic Optimization Options

Select Trim Unconnected Logic to trim unconnected components and nets from the design before mapping occurs. Deselect this option to map unconnected components and nets. Deselecting this option is useful for estimating the logic resources required for a design and for obtaining timing information on partially finished designs. When implementing an unfinished design, deselect this option to prevent partial logic from being trimmed. By default, this option is on.

Map Options

The Map Options group box contains the following options.

• CLB Packing Strategy
  
  This option partitions logic more densely. Normally, the mapper partitions logic to maximize signal sharing within CLBs and to minimize routing congestion. The CLB Packing Strategy option optimizes density by relaxing the requirement for a high degree of signal sharing between logic elements in a CLB, using the DI (direct flip-flop input) pins on CLBs, and reducing minimum signal combining requirements. The default is Fit Device.
  
  

  Note: Although the CLB Packing Strategy option makes a design denser, it can also adversely affect place and route performance, resulting in higher delays and more unrouted nets. Use this option if you are willing to trade performance for density.

  • Fit Device
    
    Select Fit Device to pack logic elements that do not share common signals into the CLBs. The mapper continues packing until the design fits into the selected device or no further packing is possible.
    
    
  • Off
    
    Select Off to disable the CLB Packing Strategy option. Disabling this option causes only related logic (logic with common inputs) to be packed together. This is useful for increasing speed in high speed designs. However, the design may overflow the selected part due to the increase in CLBs used.
    
    
• Pack CLB Registers for
  
  This option controls register ordering. When you map a design containing registers, the mapper can optimize the way the registers are grouped into CLBs. This optimized mapping is called register ordering. For more information on register ordering, see the “Register Ordering” section of the Development System Reference Guide. The default is Structure.
  
  
  • Structure
    
    Select Structure to enable register ordering. The mapper will look at the register bit names for similarities and try to map register bits in an ordered manner.
    
    
  • Minimum Area
    
    Select Minimum Area to disable register ordering for a denser design. Register bit names will be ignored when registers are mapped, and the bits will not be mapped in any special order.
    
    
• Pack I/O Registers/Latches into IOBs for
  
  This option controls the packing of flip-flops or latches within an I/O cell. Normally, the mapper packs flip-flops or latches within an I/O cell only if such packing is specified by your design entry method. This option allows you to control packing after the design entry phase. The default is Off.
  
  
  • Inputs Only
    
    Select Inputs Only to pack flip-flops or latches into input I/O cells.
    
    
  • Outputs Only
    
    Select Outputs Only to pack flip-flops or latches into output I/O cells.
    
    
  • Inputs and Outputs
    
    Select Inputs and Outputs to pack flip-flops or latches into both input and output I/O cells.
    
    
  • Off
    
    Select Off to pack flip-flops or latches as specified by your design entry method.
    
    

• Ignore RLOC Constraints
  
  Select this option to cause Map to ignore the RLOC information that contains the relative placement of one CLB to another. This option also causes Map to ignore any invalid RLOC information that would result in a Map error. By default, this option is off.
  
  

  Note: To ensure CLBs containing carry logic are aligned properly, Map retains the RLOC information that dictates what is packed into an individual CLB.

• Create Detailed Map Report
  
  Select this option to create a detailed Map report that includes signal and symbol cross-reference information. By default, this option is off.
  
  

XC3000 Place and Route Tab

Use this tab, shown in the following figure, to set the place and route options.

Figure 5.34 XC3000 Place and Route Tab

The XC3000 Place and Route tab is identical to the tab described in the “Spartan Place and Route Tab” section.

XC3000 Timing Reports Tab

Use this tab, shown in the following figure, to set the timing report options.

Figure 5.35 XC3000 Timing Reports Tab

The XC3000 Timing Reports tab is identical to the tab described in the “Spartan Timing Reports Tab” section.