Virtex Simulation Options

Click the General, VHDL/Verilog, or EDIF tab to access the different options within the Simulation Options dialog box. These options affect the timing simulation data produced during the Timing (Sim) step of the implementation flow. Use the different tabs of this dialog box to set the options described in the following sections.

Click OK to accept the options, click Cancel to exit the dialog box without changing any settings, click Default to set the default options, or click Help to obtain online help.

Virtex General Tab

Use this tab, shown in the following figure, to set the following options.

Figure 5.26 Virtex General Tab

Simulation Data Options

Specify the netlist format to use for simulation. The following formats are available.

• EDIF
  
  
• VHDL
  
  
• Verilog
  
  

Correlate Simulation Data to Input Design

Select this option to create a timing simulation netlist that contains the same logic gates and net names as those in the original schematic. Deselect this option to create a timing simulation netlist that contains the same logic gates and net names as those in the optimized implemented netlist.

Simulation Netlist Name

Select this option to specify the name of the output file. This allows you to control the output netlist name to avoid overwriting any files. The default name is time_sim.

Virtex VHDL/Verilog Tab

Use this tab, shown in the following figure, to set the VHDL or Verilog options.

Figure 5.27 Virtex VHDL/Verilog Tab

The Virtex VHDL/Verilog tab is identical to the tab described in the “Spartan VHDL/Verilog Tab” section.

Note: In Virtex devices, the following components are not reset by the GSR signal: LUT RAM, Block RAM content, DLL, and SRL.

Virtex EDIF Tab

Use the Virtex EDIF tab, shown in the following figure, to set the EDIF options.

Figure 5.28 Virtex EDIF Tab

The Virtex EDIF tab is identical to the tab described in the “Spartan EDIF Tab” section.