Features

The following sections describe the major features available in this release.

Xilinx/Cadence Interface

The following table summarizes software supplied by Cadence and Xilinx.

Table 1_1 Xilinx and Cadence Software

Libraries

The Xilinx/Cadence interface supports the Cadence 97A software release. However, to process Xilinx designs in conjunction with the 97A release, you also need the following.

To use CONCEPT2XIL from Cadence to generate EDIF netlists from Concept designs you need the following libraries from Xilinx.

• Concept Unified Libraries for schematic entry
  
  
  • spartan
    
    
  • spartanxl
    
    
  • xce3000
    
    
  • xce4000e (encompasses XC4000E/L)
    
    
  • xce4000x (encompasses XC4000EX/XL/XV)
    
    
  • xce5200
    
    
  • xce9000
    
    
  • xcepads
    
    
• VAN-Analyzed Verilog libraries (****_syn) for use by CONCEPT2XIL to create EDIF netlists
  
  
  • spartan_syn
    
    
  • spartanxl_syn
    
    
  • xce3000_syn
    
    
  • xce4000e_syn (encompasses XC4000E/L)
    
    
  • xce4000x_syn (encompasses XC4000EX/XL/XV)
    
    
  • xce5200_syn
    
    
  • xce9000_syn
    
    
• Verilog Unified Library simulation models for Verilog functional simulation
  
  
  • verilogspartan
    
    
  • verilogspartanxl
    
    
  • verilogxce3000
    
    
  • verilogxce4000e (encompasses XC4000E/L)
    
    
  • verilogxce4000x (encompasses XC4000EX/XL/XV)
    
    
  • verilogxce5200
    
    
  • verilogxce9000
    
    
• SIMPRIM-based Verilog simulation models for Verilog timing simulation and post-NGDBuild functional simulation
  
  

Schematic and Verilog Design Entry

The Xilinx/Cadence interface supports the Concept schematic design entry methodology.

Direct Generation of Structural Verilog Netlist from Concept Schematics

You can generate a Xilinx Unified Library-based structural Verilog netlist for your design directly from a Concept schematic using the Concept HDL Direct design methodology. See the “Concept Setup Library Files” section of the “Getting Started” chapter for details about how to set up your system for HDL Direct.

Standard EDIF Netlist

The Xilinx core tools read a standard EDIF 2.0.0 netlist as input. EDIF2NGD is the Xilinx tool that translates the EDIF file to a Xilinx native generic database (NGD) file. This netlisting capability simplifies integrating third party design entry and simulation tools. If you want to implement your design using the Xilinx software, you must first generate a structural Verilog netlist for your design directly from a Concept schematic using HDL Direct. (Set HDL Direct to On in Concept.) The CONCEPT2XIL netlister then converts the resulting Verilog netlists to a standard EDIF netlist.

Concept

Cadence supports two schematic editors, Concept and Composer. The Xilinx/Cadence interface for M1 supports only the Concept schematic editor.

Verilog-XL

Verilog-XL is Cadence's Verilog HDL simulator, used in the Xilinx/Cadence design flow to verify the functionality of your design. You can use Verilog-XL to perform Unified Library based functional simulation and SIMPRIM-based functional simulation. You can also use Verilog-XL for SIMPRIM-based timing simulation. You conduct timing simulation using a structural Verilog netlist and a standard delay format (SDF) file created by NGD2VER. The SDF file contains the timing data for the design.

This release supports the use of Verilog-XL to simulate behavioral Verilog, as well as Verilog gate level netlists composed of SIMPRIM elements. This release also supports gate-level simulation of LogiBLOX components. NGD2VER generates gate-level netlists.

CONCEPT2XIL

The command line program, CONCEPT2XIL, is the Cadence Concept EDIF netlister. The CONCEPT2XIL program converts the Verilog (V) file produced by Concept to an EDIF file, used as input to the Xilinx core implementation tools. Cadence Design Systems ships and supports CONCEPT2XIL.

XIL2CDS

XIL2CDS, a command line utility shipped by Cadence, allows you to integrate your chip-level design into a board level schematic.

Contact Cadence for more information about XIL2CDS.

NGD2VER

NGD2VER generates a structural SIMPRIM library-based Verilog netlist that points to the SIMPRIM library when you specify the -ul option. You can also create a design.tv testbench template file by specifying the -tf option.You can use the template to create a testbench to verify your design. If timing information exists in a mapped or routed NGA file, NGD2VER also generates an SDF file.

Simulation of Synopsys Designs

The Xilinx/Cadence interface supports RTL, Post-NGDBuild, Post-MAP, and timing simulation of Synopsys designs entered in Verilog HDL. For more information, refer to the “Synopsys/Verilog Design Flow” appendix.

Automatic Library Specification

NGD2VER generates the Verilog-XL `uselib statement in your Verilog netlist referencing the SIMPRIM library when you specify the -ul option.

Waveform Viewer Support

NGD2VER can add support for the Cadence SimWave Waveform Viewer by writing out $shm_open and $shm_probe directives to your Verilog netlist, creating a simulation history manager (SHM) database. The test fixture (.tv extension) created by NGD2VER incorporates the SHM directives.

LogiBLOX

Use LogiBLOX, a Xilinx tool, to create high-level functional modules you can incorporate into a schematic or an HDL-based design. LogiBLOX works only in standalone mode for the Cadence interface. After you create your modules, you must use the Concept genview command to generate bodies for your modules. See the “Processing Designs with LogiBLOX Components” appendix for details.

Timing Constraints

You can specify timing constraints in your Concept schematic to guide the place and route tools. You can later add timing constraints as properties. For details about timing constraints, refer to the “Using Timing Constraints” chapter in the Development System Reference Guide.

You can also place constraints in an external constraints file (*.ucf extension) that EDIF2NGD can process. For details on user constraint files, refer to the Development System Reference Guide.