After you complete and save your design schematics, you automatically have an HDL Direct-generated Verilog netlist for every block in your design. Use the CONCEPT2XIL program with the -sim_only option to configure these Verilog netlists so that you can perform a functional simulation. Refer to the “Functional Simulation” chapter for details.
After completing functional simulation, use CONCEPT2XIL to prepare your design for use with the Xilinx design implementation tools. Refer to the “Converting the Concept Design to an EDIF File” section of the “Design Implementation” chapter for details.
