Chapter 4

Functional Simulation

This chapter explains how to perform functional simulation on your Concept designs using Verilog-XL. Functional simulation provides an effective means of identifying logic errors in your design before implementing the design in a Xilinx device. Because timing information for the design is not available in a functional simulation, conduct your functional simulation using unit delays. Performing functional simulation before routing your design saves debugging time later in the design process by verifying that your design is functionally correct.

This chapter contains the following sections.

• “Unified Library-Based Functional Simulation”
  
  
• “SIMPRIM Library-Based Functional Simulation”
  
  

Additionally, this chapter describes two types of functional simulation.

• Unified Library-Based Functional Simulation
  
  You perform this simulation on the output Verilog files from Concept HDL Direct and the Verilog configuration file (VF) for a purely schematic design, following a post-processing step by CONCEPT2XIL. See the “Unified Library Based Functional Simulation” figure.
  
  
• SIMPRIM-Based Functional Simulation
  
  

You perform this simulation on V and TV (option -tf for NGD2VER) files created by NGD2VER on the NGD file output from NGDBuild. You can perform SIMPRIM-based functional simulation on any type of design (the only available method on mixed-mode designs). See the “SIMPRIM-Based Functional Simulation” figure.

You can usually perform both types of simulation on either FPGA or CPLD designs. There is no simulation modeling for boundary scan or readback.

Figure 4.1 Unified Library Based Functional Simulation