Timing simulation verifies a placed and routed design by using worst-case routing and block delay information. Use the delay information, extracted from the routed design and passed to the back-annotated simulation netlist, during timing simulation. Timing simulation reduces the need for hardware debugging by determining whether or not the design works under worst-case conditions.
Use timing simulation to determining the device speed grade required for a particular application. Timing simulation verifies design functionality by using delay information from the routed .ncd file created during design implementation.
Do not use the timing simulation netlist as an absolute representation of the placed and routed design. While logic structure modeling shows the same functionality and timing (from a pad or synchronous source to a pad or synchronous destination) as the implemented design, delay distribution along this path can differ. Additionally, the logic structures and paths do not necessarily reflect what implements in the silicon. Use this generated netlist solely for the purpose of simulating the design.
This chapter describes how to prepare for timing simulation using the NGD2VER command and conduct timing simulation within the Cadence simulation environment using Verilog-XL. Additionally, this chapter describes how to load SimWave to view the simulation signals in a waveform format.
This chapter contains these sections.
There is no simulation modeling for boundary scan or readback.
