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Timing Simulation

This section explains how to conduct post-map and post-implementation timing simulations.

Post-Map Timing Simulation (FPGAs Only)

Before performing a post-map timing simulation, you require a mapped and back-annotated netlist for your design. After generating those, perform the following steps.

  1. Run NGDAnno to obtain a back-annotated netlist.

    ngdanno design design_m [design.ngm]

  2. Use NGD2VER to create a structural Verilog netlist and a testbench stimulus template.

    ngd2ver [-tf] -ul design_m.[nga]

    You need the -tf option only if you did not generate a testbench template during functional simulation.

  3. Make a copy of the testbench stimulus template and edit it to create a user-specified testbench file.

  4. Invoke Verilog-XL with the following command.

verilog  full_path_to_designt.stim full_path_to_designt.v

Post-Implementation Timing Simulation

For FPGAs, you must map, route, and back-annotate your design. For CPLDs, you must run the design through the CPLD fitter.

  1. For FPGAs, use NGDAnno to back-annotate your design. Assuming the routed NCD file is called “designt,” enter the following command.

    ngdanno designt design.ngm

    If designing for a CPLD, use the NGA file output from the CPLD Fitter as an input to the NGD2VER command in the next step.

  2. Use NGD2VER to create a structural Verilog netlist and a testbench stimulus template.

    ngd2ver -tf -ul [-pf] design_name.nga design_namet.v

    You need the -pf option only if you plan to integrate the design into a board-level schematic.

    Rename the output to design_namet to avoid overwriting any simulation netlists generated for Unified Library functional simulation. Refer to the “Running NGD2VER” section of the “Timing Simulation” chapter.

  3. Make a copy of the testbench template, naming it designt.stim and add your test vectors to the copy. Use the copy as your testbench file.

  4. Submit the design to the Cadence Verilog-XL simulator to conduct a timing simulation.

verilog  full_path_to_designt.stim  full_path_to_designt.v

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