Updated tutorials are available after June 30, 1998 from the Xilinx Web site and on the AppLINX CD. The Web site location is (http://www.xilinx.com/support/techsup/tutorials). Please contact your local Sales Representative for a copy of the AppLINX CD.
This chapter guides you through a typical Field Programmable Gate Array (FPGA) and Complex Programmable Logic Device (CPLD) design procedure from schematic entry to completion of a functioning device. It uses a design called Calc, a 4-bit processor with a stack. In the first part of the tutorial, you use Concept, the Cadence design entry tool, to create the schematics and symbols for the Calc design. Next you use Verilog-XL, the Cadence Verilog HDL simulator, to perform a functional simulation on the design. In the third step, you use the Xilinx Design Manager to implement the design. Finally, you verify the design's timing by again using Verilog-XL. The simple design example used in this tutorial demonstrates many system features that you can apply to more complex FPGA and CPLD designs as well.
Although this tutorial describes creating and processing FPGA designs, you can apply most of the steps to CPLD designs.
This tutorial includes instructions on the following.
This chapter contains the following sections.
