Appendix C

Mentor Graphics Interface Notes

This appendix describes how to set up the Mentor Graphics interface and associated libraries. You are guided through examples on pin locking and timing constraints. This chapter includes the following sections.

Additional Documentation

The following documentation is available for the Mentor Graphics interface.

Mentor Graphics Interface/Tutorial Guide is available online and viewable with a DynaText browser.
Mentor Graphics software documentation (for applications such as Design Architect, QuickSim, QuickHDL, and DVE) is available online and viewable with the Mentor-supplied BOLD Browser.
Alliance 1.5 Release Documentation describes installation setup and current issues regarding the use of the Mentor Graphics Interface.

Setting Up the Xilinx/Mentor Interface

In addition to the environment variables discussed in the “Installing the Software” chapter, the following environment variables must be modified or added to run the Xilinx/Mentor interface tools.

MGC_HOME (add)
LCA (add)
SIMPRIMS (add)
MGC_GENLIB (add)
MGC_LOCATION_MAP (add)
path (modify)
LD_LIBRARY_PATH (modify for Solaris)
SHLIB_PATH (modify for HP-UX)

Set these variables as follows.

setenv MGC_HOME <installation_path_to_mentor>

setenv LCA $XILINX/mentor/data

setenv MGC_GENLIB $MGC_HOME/gen_lib

setenv MGC_LOCATION_MAP <location_of_actual_map_file>

set path = ($XILINX/mentor/bin/<platform_name> \

 $path)

For Solaris only.

setenv LD_LIBRARY_PATH $MGC_HOME/shared/lib:$MGC_HOME/lib:$LD_LIBRARY_PATH

For HP-UX only.

setenv SHLIB_PATH $MGC_HOME/shared/lib:$MGC_HOME/lib:$SHLIB_PATH

The following is an example of how to set the environment variables.

setenv MGC_HOME /usr/mentor

setenv LCA $XILINX/mentor/data

setenv SIMPRIMS $LCA/simprims

setenv MGC_GENLIB $MGC_HOME/gen_lib

setenv MGC_LOCATION_MAP /usr/data/mgc_location_map

set path = ($XILINX/mentor/bin/sol $path)

setenv LD_LIBRARY_PATH $MGC_HOME/shared/lib:$MGC_HOME/lib:$LD_LIBRARY_PATH

NOTE

The previous settings assume that the Xilinx environment variables point to the appropriate area, as described in the “Installing the Software” chapter.

Mentor/Xilinx Software Design Flow

The following figure illustrates the Mentor Graphics and Xilinx software design flow. Shown are design entry, functional simulation, implementation, and timing simulation.

Figure C.1 Mentor/Xilinx Software Flow

The design flow starts with design entry with PLD_DA (the Mentor schematic design tool).
The design is processed by PLD_DVE to generate a Xilinx-style design viewpoint.
The design is then passed to PLD_QuickSim for functional simulation.
Once the design logic has been verified, the Mentor schematic is processed by PLD_MEN2EDIF to create an EDIF file.
The EDIF file is passed to the Xilinx tools for implementation.
The Xilinx tools create an EDN file that is processed by PLD_EDIF2TIM to create a timing-annotated EDDM netlist.
This new netlist is processed by PLD_DVE to generate a Xilinx style design viewpoint.
The design is passed to PLD_QuickSim to run in cross-probing mode for timing simulation.

For functional simulation, first generate a simulation viewpoint, with PLD_DVE. For example, to generate a viewpoint for the XC4000EX component my_design, use the following command.

pld_dve -s my_design xc4000ex

A specific viewpoint name can optionally be given after the technology type. If one is not given, a default viewpoint is created with the name default.

To simulate this design, use the following command.

pld_quicksim my_design

This runs QuickSim for functional simulation without cross-probing.

You may also use the PLD_DVE and PLD_QuickSim icons in PLD_DMGR. For more information on functional simulation, see the Mentor Graphics Interface/Tutorial Guide.

Translating a Design to Xilinx EDIF

To translate a design into an EDIF file for the Xilinx implementation tools, use the PLD_MEN2EDIF command. For example, to target my_design to the XC4000EX.

pld_men2edif my_design xc4000ex

You may also specify a viewpoint name after the technology type. If a viewpoint name is not given, a default viewpoint is used with the name default. This default viewpoint name is the same as that used by PLD_DVE.

You may also use the pld_men2edif icon in PLD_DMGR. For more information on PLD_MEN2EDIF, see the Mentor Graphics Interface/Tutorial Guide.

Timing Simulation

After implementing your design and generating an annotated NGA netlist (with NGDANNO), you must use NGD2EDIF to generate a timing-annotated EDIF netlist that Mentor can use.

Generating a Timing-Annotated EDIF Netlist

Use NGD2EDIF to generate a timing-annotated EDIF netlist. In the case of my_design, for example, enter the following.

ngd2edif -v mentor my_design.nga my_design.edn

This creates an EDN file compatible with the Mentor interface.

Generating a Timing Model

After creating the EDN file, run PLD_EDIF2TIM to generate a timing model with the following command.

pld_edif2tim my_design.edn

This creates an EDDM-type component under my_design_lib/my_design, as well as a simulation viewpoint for that component.

Running PLD_QuickSim

After generating the simulation viewpoint, run PLD_QuickSim with cross-probing on this new component. (If you do not wish to annotate simulation values onto your original schematic, you may remove the -cp option to run without cross-probing.)

pld_quicksim my_design_lib/my design

-cp -tim type -consm messages

QuickSim will start up and read in the new timing-annotated EDDM netlist. DVE will also start up. Open the viewpoint and schematic sheet for your original schematic in DVE to annotate simulation values (from QuickSim) onto that front-end schematic.

You may also use the PLD_EDIF2TIM and PLD_QuickSim icons in PLD_DMGR. For more information on timing simulation, including a more detailed explanation on cross-probing, see the Mentor Graphics Interface/Tutorial Guide.

Mentor Interface Environment Variables

Set the following environment variables.

setenv LCA $XILINX/mentor/data
   setenv SIMPRIMS $LCA/simprims
   set path = ($XILINX/mentor/bin/sol $path)

(This example is for Solaris workstations. Replace “sol” with “hp” for HP-UX workstations.) These variables are in addition to the XILINX environment variable settings required by the Alliance Series Design Implementation Tools. To refer to the Mentor-specific variables such as MGC_HOME and MGC_LOCATION_MAP, see the Mentor Graphics Interface/Tutorial Guide for more information.

Library Locations and Sample MGC Location Map

All Xilinx libraries reside under the $LCA directory as with XACT 5.x. Also underneath this directory is the “simprims” (simulation primitives) library that QuickSim must use to simulate back-end timing simulation models. This requires your MGC location map to have the following lines in addition to any other soft names (including MGC_GENLIB) you have included.

MGC_LOCATION_MAP_1

$LCA
   (blank line)

$SIMPRIMS
   (blank line)

As always, your $MGC_LOCATION_MAP file points to the location of this file. For more information on location maps, see the Mentor Graphics Interface/Tutorial Guide.

Pin Locking

Pad symbols (IPAD, OPAD, etc.) have generic pin-location (“LOC”) properties already attached to them. (They appear as “PXX” on the pad symbol.) You can place pads in specific locations on the device by modifying these properties as required. (An example property value for a pad symbol may be “P24”.) Note that “bused” pad symbols (for example, IPAD8) may take a comma-separated list (in MSB to LSB order) of locations (P24, P23, P22, . . . ). For more information on location constraints, see the Libraries Guide.

Timing Constraints

Timing constraints can be placed as properties on a TIMESPEC symbol in the design. The Timespec label (the label that begins with “TS”) is entered as the property name, while the timing specification (for example, “FROM:FFS:TO:FFS=30NS”) is entered as the property value. For more information on timing constraints, see the Development System Reference Guide.